Xingyu Wu 61f2e8a3a9 riscv: dts: starfive: jh7110-common: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz ...

CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz.
But now PLL0 rate is 1GHz and the cpu frequency loads become
250/333/500/1000MHz in fact.

The PLL0 rate should be default set to 1.5GHz and set the
cpu_core rate to 500MHz in safe.

Fixes: e2c510d6d6 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC")
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

2024-09-08 23:20:19 +01:00

..

dts

riscv: dts: starfive: jh7110-common: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz

2024-09-08 23:20:19 +01:00

.gitignore

riscv: efi: enable generic EFI compressed boot

2022-09-20 09:50:30 +02:00

install.sh

kbuild: Abort make on install failures

2024-07-20 13:34:54 +09:00

loader.lds.S

riscv: Move kernel mapping outside of linear mapping

2021-04-26 08:25:04 -07:00

loader.S

riscv: provide a flat image loader

2019-11-17 15:17:39 -08:00

Makefile

riscv: boot: remove duplicated targets line

2024-07-24 06:14:06 -07:00