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0049618433
Conor Dooley <conor@kernel.org> says: From: Conor Dooley <conor.dooley@microchip.com> Yo, This series is partly leveraging Clement's work adding a validate callback in the extension detection code so that things like checking for whether a vector crypto extension is usable can be done like: has_extension(<vector crypto>) rather than has_vector() && has_extension(<vector crypto>) which Eric pointed out was a poor design some months ago. The rest of this is adding some requirements to the bindings that prevent combinations of extensions disallowed by the ISA. There's a bunch of over-long lines in here, but I thought that the over-long lines were clearer than breaking them up. Cheers, Conor. * patches from https://lore.kernel.org/r/20250312-abide-pancreas-3576b8c44d2c@spud: dt-bindings: riscv: document vector crypto requirements dt-bindings: riscv: add vector sub-extension dependencies dt-bindings: riscv: d requires f RISC-V: add f & d extension validation checks RISC-V: add vector crypto extension validation checks RISC-V: add vector extension validation checks Link: https://lore.kernel.org/r/20250312-abide-pancreas-3576b8c44d2c@spud Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
144 lines
4.3 KiB
C
144 lines
4.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright 2022-2024 Rivos, Inc
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*/
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#ifndef _ASM_CPUFEATURE_H
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#define _ASM_CPUFEATURE_H
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#include <linux/bitmap.h>
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#include <linux/jump_label.h>
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#include <linux/workqueue.h>
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#include <linux/kconfig.h>
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#include <linux/percpu-defs.h>
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#include <linux/threads.h>
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#include <asm/hwcap.h>
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#include <asm/cpufeature-macros.h>
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/*
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* These are probed via a device_initcall(), via either the SBI or directly
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* from the corresponding CSRs.
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*/
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struct riscv_cpuinfo {
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unsigned long mvendorid;
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unsigned long marchid;
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unsigned long mimpid;
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};
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struct riscv_isainfo {
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DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX);
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};
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DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
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/* Per-cpu ISA extensions. */
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extern struct riscv_isainfo hart_isa[NR_CPUS];
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extern u32 thead_vlenb_of;
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void __init riscv_user_isa_enable(void);
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#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size, _validate) { \
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.name = #_name, \
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.property = #_name, \
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.id = _id, \
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.subset_ext_ids = _subset_exts, \
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.subset_ext_size = _subset_exts_size, \
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.validate = _validate \
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}
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#define __RISCV_ISA_EXT_DATA(_name, _id) _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0, NULL)
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#define __RISCV_ISA_EXT_DATA_VALIDATE(_name, _id, _validate) \
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_RISCV_ISA_EXT_DATA(_name, _id, NULL, 0, _validate)
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/* Used to declare pure "lasso" extension (Zk for instance) */
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#define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \
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_RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, \
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ARRAY_SIZE(_bundled_exts), NULL)
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#define __RISCV_ISA_EXT_BUNDLE_VALIDATE(_name, _bundled_exts, _validate) \
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_RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, \
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ARRAY_SIZE(_bundled_exts), _validate)
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/* Used to declare extensions that are a superset of other extensions (Zvbb for instance) */
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#define __RISCV_ISA_EXT_SUPERSET(_name, _id, _sub_exts) \
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_RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), NULL)
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#define __RISCV_ISA_EXT_SUPERSET_VALIDATE(_name, _id, _sub_exts, _validate) \
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_RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), _validate)
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bool __init check_unaligned_access_emulated_all_cpus(void);
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#if defined(CONFIG_RISCV_SCALAR_MISALIGNED)
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void check_unaligned_access_emulated(struct work_struct *work __always_unused);
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void unaligned_emulation_finish(void);
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bool unaligned_ctl_available(void);
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DECLARE_PER_CPU(long, misaligned_access_speed);
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#else
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static inline bool unaligned_ctl_available(void)
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{
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return false;
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}
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#endif
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bool __init check_vector_unaligned_access_emulated_all_cpus(void);
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#if defined(CONFIG_RISCV_VECTOR_MISALIGNED)
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void check_vector_unaligned_access_emulated(struct work_struct *work __always_unused);
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DECLARE_PER_CPU(long, vector_misaligned_access);
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#endif
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#if defined(CONFIG_RISCV_PROBE_UNALIGNED_ACCESS)
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DECLARE_STATIC_KEY_FALSE(fast_unaligned_access_speed_key);
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static __always_inline bool has_fast_unaligned_accesses(void)
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{
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return static_branch_likely(&fast_unaligned_access_speed_key);
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}
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#else
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static __always_inline bool has_fast_unaligned_accesses(void)
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{
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if (IS_ENABLED(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS))
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return true;
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else
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return false;
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}
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#endif
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unsigned long riscv_get_elf_hwcap(void);
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struct riscv_isa_ext_data {
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const unsigned int id;
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const char *name;
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const char *property;
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const unsigned int *subset_ext_ids;
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const unsigned int subset_ext_size;
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int (*validate)(const struct riscv_isa_ext_data *data, const unsigned long *isa_bitmap);
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};
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extern const struct riscv_isa_ext_data riscv_isa_ext[];
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extern const size_t riscv_isa_ext_count;
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extern bool riscv_isa_fallback;
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unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
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static __always_inline bool riscv_cpu_has_extension_likely(int cpu, const unsigned long ext)
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{
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compiletime_assert(ext < RISCV_ISA_EXT_MAX, "ext must be < RISCV_ISA_EXT_MAX");
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if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) &&
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__riscv_has_extension_likely(STANDARD_EXT, ext))
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return true;
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return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
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}
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static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsigned long ext)
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{
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compiletime_assert(ext < RISCV_ISA_EXT_MAX, "ext must be < RISCV_ISA_EXT_MAX");
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if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) &&
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__riscv_has_extension_unlikely(STANDARD_EXT, ext))
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return true;
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return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
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}
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#endif
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