Files
linux/drivers/gpu/drm/amd/include/asic_reg
fanhuang 80f66ca7a4 drm/amdgpu: add vcn v5_0_0 ip headers
Add vcn v5_0_0 register offset and shift masks
header files
Only include the registers required for MMSCH
initialization

Signed-off-by: fanhuang <FangSheng.Huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-05-13 09:31:51 -04:00
..
2024-07-23 17:33:17 -04:00
2025-04-07 15:18:33 -04:00
2017-03-29 23:52:57 -04:00
2025-05-13 09:31:51 -04:00
2020-03-06 14:31:21 -05:00