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c026565fe9
Enable one additional plane that is alpha blended on top of the primary plane. This also fixes the below warnings when building with -Warray-bounds: drivers/gpu/drm/kmb/kmb_plane.c:135:20: warning: array subscript 3 is above array bounds of 'struct layer_status[1]' [-Warray-bounds] drivers/gpu/drm/kmb/kmb_plane.c:132:20: warning: array subscript 2 is above array bounds of 'struct layer_status[1]' [-Warray-bounds] drivers/gpu/drm/kmb/kmb_plane.c:129:20: warning: array subscript 1 is above array bounds of 'struct layer_status[1]' [-Warray-bounds] v2: corrected previous patch dependecies so it builds Signed-off-by: Edmund Dea <edmund.j.dea@intel.com> Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus@intel.com> Acked-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.kernel.org/project/dri-devel/patch/20210728003126.1425028-13-anitha.chrisanthus@intel.com/ Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
99 lines
2.3 KiB
C
99 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only
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*
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* Copyright © 2018-2020 Intel Corporation
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*/
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#ifndef __KMB_DRV_H__
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#define __KMB_DRV_H__
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#include <drm/drm_device.h>
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#include "kmb_plane.h"
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#include "kmb_regs.h"
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#define KMB_MAX_WIDTH 1920 /*Max width in pixels */
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#define KMB_MAX_HEIGHT 1080 /*Max height in pixels */
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#define KMB_MIN_WIDTH 1920 /*Max width in pixels */
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#define KMB_MIN_HEIGHT 1080 /*Max height in pixels */
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#define DRIVER_DATE "20210223"
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#define DRIVER_MAJOR 1
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#define DRIVER_MINOR 1
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#define KMB_FB_MAX_WIDTH 1920
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#define KMB_FB_MAX_HEIGHT 1080
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#define KMB_FB_MIN_WIDTH 1
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#define KMB_FB_MIN_HEIGHT 1
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#define KMB_LCD_DEFAULT_CLK 200000000
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#define KMB_SYS_CLK_MHZ 500
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#define ICAM_MMIO 0x3b100000
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#define ICAM_LCD_OFFSET 0x1080
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#define ICAM_MMIO_SIZE 0x2000
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struct kmb_dsi;
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struct kmb_clock {
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struct clk *clk_lcd;
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struct clk *clk_pll0;
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};
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struct kmb_drm_private {
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struct drm_device drm;
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struct kmb_dsi *kmb_dsi;
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void __iomem *lcd_mmio;
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struct kmb_clock kmb_clk;
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struct drm_crtc crtc;
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struct kmb_plane *plane;
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struct drm_atomic_state *state;
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spinlock_t irq_lock;
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int irq_lcd;
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int sys_clk_mhz;
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struct layer_status plane_status[KMB_MAX_PLANES];
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int kmb_under_flow;
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int kmb_flush_done;
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int layer_no;
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};
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static inline struct kmb_drm_private *to_kmb(const struct drm_device *dev)
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{
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return container_of(dev, struct kmb_drm_private, drm);
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}
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static inline struct kmb_drm_private *crtc_to_kmb_priv(const struct drm_crtc *x)
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{
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return container_of(x, struct kmb_drm_private, crtc);
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}
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static inline void kmb_write_lcd(struct kmb_drm_private *dev_p,
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unsigned int reg, u32 value)
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{
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writel(value, (dev_p->lcd_mmio + reg));
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}
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static inline u32 kmb_read_lcd(struct kmb_drm_private *dev_p, unsigned int reg)
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{
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return readl(dev_p->lcd_mmio + reg);
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}
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static inline void kmb_set_bitmask_lcd(struct kmb_drm_private *dev_p,
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unsigned int reg, u32 mask)
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{
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u32 reg_val = kmb_read_lcd(dev_p, reg);
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kmb_write_lcd(dev_p, reg, (reg_val | mask));
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}
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static inline void kmb_clr_bitmask_lcd(struct kmb_drm_private *dev_p,
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unsigned int reg, u32 mask)
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{
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u32 reg_val = kmb_read_lcd(dev_p, reg);
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kmb_write_lcd(dev_p, reg, (reg_val & (~mask)));
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}
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int kmb_setup_crtc(struct drm_device *dev);
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void kmb_set_scanout(struct kmb_drm_private *lcd);
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#endif /* __KMB_DRV_H__ */
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