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6f8b7565cc
[Why & How] Add HWSEQ handling for DCN35. Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
83 lines
3.0 KiB
C
83 lines
3.0 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright 2023 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __DC_HWSS_DCN35_H__
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#define __DC_HWSS_DCN35_H__
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#include "hw_sequencer_private.h"
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struct dc;
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void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
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void dcn35_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on);
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void dcn35_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);
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void dcn35_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);
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void dcn35_set_dmu_fgcg(struct dce_hwseq *hws, bool enable);
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void dcn35_init_hw(struct dc *dc);
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void dcn35_disable_link_output(struct dc_link *link,
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const struct link_resource *link_res,
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enum signal_type signal);
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void dcn35_power_down_on_boot(struct dc *dc);
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bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable);
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void dcn35_z10_restore(const struct dc *dc);
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void dcn35_init_pipes(struct dc *dc, struct dc_state *context);
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void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);
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void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,
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struct dc_state *context);
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void dcn35_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);
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void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,
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struct pg_block_update *update_state);
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void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,
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struct pg_block_update *update_state);
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void dcn35_block_power_control(struct dc *dc,
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struct pg_block_update *update_state, bool power_on);
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void dcn35_root_clock_control(struct dc *dc,
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struct pg_block_update *update_state, bool power_on);
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void dcn35_prepare_bandwidth(
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struct dc *dc,
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struct dc_state *context);
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void dcn35_optimize_bandwidth(
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struct dc *dc,
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struct dc_state *context);
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void dcn35_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable);
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void dcn35_dsc_pg_control(
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struct dce_hwseq *hws,
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unsigned int dsc_inst,
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bool power_on);
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#endif /* __DC_HWSS_DCN35_H__ */
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