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Memory barriers are building blocks for concurrent code, hence provide a minimal set of them. The compiler barrier, barrier(), is implemented in inline asm instead of using core::sync::atomic::compiler_fence() because memory models are different: kernel's atomics are implemented in inline asm therefore the compiler barrier should be implemented in inline asm as well. Also it's currently only public to the kernel crate until there's a reasonable driver usage. Signed-off-by: Boqun Feng <boqun.feng@gmail.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Alice Ryhl <aliceryhl@google.com> Reviewed-by: Elle Rhumsaa <elle@weathered-steel.dev> Link: https://lore.kernel.org/all/20250719030827.61357-10-boqun.feng@gmail.com/
19 lines
204 B
C
19 lines
204 B
C
// SPDX-License-Identifier: GPL-2.0
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#include <asm/barrier.h>
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void rust_helper_smp_mb(void)
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{
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smp_mb();
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}
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void rust_helper_smp_wmb(void)
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{
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smp_wmb();
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}
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void rust_helper_smp_rmb(void)
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{
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smp_rmb();
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}
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