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[ Upstream commit4c85e20b65] All the various MediaTek clock drivers are, in a way or another, redefining the GATE_MTK() macro with different names: while some are doing that by actually using GATE_MTK(), others are copying it entirely (hence, entirely redefining it). Change all clock drivers to always and consistently use this macro. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Chen-Yu Tsai <wenst@chromium.org> # MT8183, MT8192, MT8195 Chromebooks Link: https://lore.kernel.org/r/20230306140543.1813621-23-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> Stable-dep-of:fa8c0d01df("clk: mediatek: mt7622: Properly use CLK_IS_CRITICAL flag") Signed-off-by: Sasha Levin <sashal@kernel.org>
52 lines
1.1 KiB
C
52 lines
1.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2017 MediaTek Inc.
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* Author: Weiyi Lu <weiyi.lu@mediatek.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt2712-clk.h>
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static const struct mtk_gate_regs mfg_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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#define GATE_MFG(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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static const struct mtk_gate mfg_clks[] = {
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GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
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};
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static const struct mtk_clk_desc mfg_desc = {
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.clks = mfg_clks,
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.num_clks = ARRAY_SIZE(mfg_clks),
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};
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static const struct of_device_id of_match_clk_mt2712_mfg[] = {
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{
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.compatible = "mediatek,mt2712-mfgcfg",
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.data = &mfg_desc,
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}, {
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/* sentinel */
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}
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};
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static struct platform_driver clk_mt2712_mfg_drv = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt2712-mfg",
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.of_match_table = of_match_clk_mt2712_mfg,
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},
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};
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builtin_platform_driver(clk_mt2712_mfg_drv);
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