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[ Upstream commit4c85e20b65] All the various MediaTek clock drivers are, in a way or another, redefining the GATE_MTK() macro with different names: while some are doing that by actually using GATE_MTK(), others are copying it entirely (hence, entirely redefining it). Change all clock drivers to always and consistently use this macro. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Chen-Yu Tsai <wenst@chromium.org> # MT8183, MT8192, MT8195 Chromebooks Link: https://lore.kernel.org/r/20230306140543.1813621-23-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> Stable-dep-of:fa8c0d01df("clk: mediatek: mt7622: Properly use CLK_IS_CRITICAL flag") Signed-off-by: Sasha Levin <sashal@kernel.org>
60 lines
1.9 KiB
C
60 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: James Liao <jamesjj.liao@mediatek.com>
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* Fabien Parent <fparent@baylibre.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt8516-clk.h>
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static const struct mtk_gate_regs aud_cg_regs = {
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.set_ofs = 0x0,
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.clr_ofs = 0x0,
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.sta_ofs = 0x0,
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};
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#define GATE_AUD(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &aud_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
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static const struct mtk_gate aud_clks[] __initconst = {
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GATE_AUD(CLK_AUD_AFE, "aud_afe", "clk26m_ck", 2),
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GATE_AUD(CLK_AUD_I2S, "aud_i2s", "i2s_infra_bck", 6),
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GATE_AUD(CLK_AUD_22M, "aud_22m", "rg_aud_engen1", 8),
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GATE_AUD(CLK_AUD_24M, "aud_24m", "rg_aud_engen2", 9),
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GATE_AUD(CLK_AUD_INTDIR, "aud_intdir", "rg_aud_spdif_in", 15),
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GATE_AUD(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "rg_aud_engen2", 18),
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GATE_AUD(CLK_AUD_APLL_TUNER, "aud_apll_tuner", "rg_aud_engen1", 19),
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GATE_AUD(CLK_AUD_HDMI, "aud_hdmi", "apll12_div4", 20),
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GATE_AUD(CLK_AUD_SPDF, "aud_spdf", "apll12_div6", 21),
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GATE_AUD(CLK_AUD_ADC, "aud_adc", "aud_afe", 24),
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GATE_AUD(CLK_AUD_DAC, "aud_dac", "aud_afe", 25),
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GATE_AUD(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "aud_afe", 26),
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GATE_AUD(CLK_AUD_TML, "aud_tml", "aud_afe", 27),
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};
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static void __init mtk_audsys_init(struct device_node *node)
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{
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struct clk_hw_onecell_data *clk_data;
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int r;
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clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
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mtk_clk_register_gates(NULL, node, aud_clks, ARRAY_SIZE(aud_clks), clk_data);
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r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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}
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CLK_OF_DECLARE(mtk_audsys, "mediatek,mt8516-audsys", mtk_audsys_init);
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