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Add support for wrapper settings for DSI bridge on j721e. Also enable DPI0 --------------- ----------------------- | -------| |------- | | DSS | DPI2 |----->| DPI0 | DSI Wrapper | | -------| |------- | --------------- ----------------------- As shown above DPI2 output of DSS is connected to DPI0 input of DSI Wrapper, DSI wrapper gives control wheather to enable/disable DPI0 input. In j721e above is the only configuration supported Signed-off-by: Rahul T R <r-ravikumar@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230103101951.10963-6-r-ravikumar@ti.com
49 lines
1.3 KiB
Plaintext
49 lines
1.3 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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config DRM_CDNS_DSI
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tristate "Cadence DPI/DSI bridge"
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select DRM_KMS_HELPER
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select DRM_MIPI_DSI
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select DRM_PANEL_BRIDGE
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select GENERIC_PHY_MIPI_DPHY
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depends on OF
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help
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Support Cadence DPI to DSI bridge. This is an internal
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bridge and is meant to be directly embedded in a SoC.
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if DRM_CDNS_DSI
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config DRM_CDNS_DSI_J721E
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bool "J721E Cadence DSI wrapper support"
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default y
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help
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Support J721E Cadence DSI wrapper. The wrapper manages
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the routing of the DSS DPI signal to the Cadence DSI.
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endif
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config DRM_CDNS_MHDP8546
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tristate "Cadence DPI/DP bridge"
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select DRM_DISPLAY_DP_HELPER
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select DRM_DISPLAY_HDCP_HELPER
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select DRM_DISPLAY_HELPER
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select DRM_KMS_HELPER
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select DRM_PANEL_BRIDGE
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depends on OF
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help
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Support Cadence DPI to DP bridge. This is an internal
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bridge and is meant to be directly embedded in a SoC.
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It takes a DPI stream as input and outputs it encoded
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in DP format.
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if DRM_CDNS_MHDP8546
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config DRM_CDNS_MHDP8546_J721E
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depends on ARCH_K3 || COMPILE_TEST
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bool "J721E Cadence DPI/DP wrapper support"
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default y
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help
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Support J721E Cadence DPI/DP wrapper. This is a wrapper
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which adds support for J721E related platform ops. It
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initializes the J721E Display Port and sets up the
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clock and data muxes.
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endif
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