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0e7f270591
By default, HBR2 (5.4G) is the max link rate be supported. This patch uses the actual limit specified by DT and removes the artificial limitation to 5.4 Gbps. Supporting HBR3 is a consequence of that. Changes in v2: -- add max link rate from dtsi Changes in v3: -- parser max_data_lanes and max_dp_link_rate from dp_out endpoint Changes in v4: -- delete unnecessary pr_err Changes in v5: -- split parser function into different patch Changes in v9: -- revised commit test Changes in v13: -- repalced "properity" with "property" Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/516097/ Link: https://lore.kernel.org/r/1672163103-31254-6-git-send-email-quic_khsieh@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
101 lines
2.4 KiB
C
101 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DP_PANEL_H_
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#define _DP_PANEL_H_
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#include <drm/msm_drm.h>
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#include "dp_aux.h"
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#include "dp_link.h"
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#include "dp_hpd.h"
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struct edid;
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#define DPRX_EXTENDED_DPCD_FIELD 0x2200
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#define DP_DOWNSTREAM_PORTS 4
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#define DP_DOWNSTREAM_CAP_SIZE 4
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struct dp_display_mode {
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struct drm_display_mode drm_mode;
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u32 capabilities;
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u32 bpp;
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u32 h_active_low;
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u32 v_active_low;
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};
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struct dp_panel_in {
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struct device *dev;
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struct drm_dp_aux *aux;
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struct dp_link *link;
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struct dp_catalog *catalog;
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};
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struct dp_panel {
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/* dpcd raw data */
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u8 dpcd[DP_RECEIVER_CAP_SIZE + 1];
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u8 ds_cap_info[DP_DOWNSTREAM_PORTS * DP_DOWNSTREAM_CAP_SIZE];
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u32 ds_port_cnt;
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u32 dfp_present;
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struct dp_link_info link_info;
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struct drm_dp_desc desc;
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struct edid *edid;
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struct drm_connector *connector;
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struct dp_display_mode dp_mode;
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bool video_test;
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u32 vic;
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u32 max_dp_lanes;
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u32 max_dp_link_rate;
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u32 max_bw_code;
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};
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int dp_panel_init_panel_info(struct dp_panel *dp_panel);
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int dp_panel_deinit(struct dp_panel *dp_panel);
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int dp_panel_timing_cfg(struct dp_panel *dp_panel);
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void dp_panel_dump_regs(struct dp_panel *dp_panel);
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int dp_panel_read_sink_caps(struct dp_panel *dp_panel,
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struct drm_connector *connector);
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u32 dp_panel_get_mode_bpp(struct dp_panel *dp_panel, u32 mode_max_bpp,
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u32 mode_pclk_khz);
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int dp_panel_get_modes(struct dp_panel *dp_panel,
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struct drm_connector *connector);
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void dp_panel_handle_sink_request(struct dp_panel *dp_panel);
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void dp_panel_tpg_config(struct dp_panel *dp_panel, bool enable);
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/**
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* is_link_rate_valid() - validates the link rate
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* @lane_rate: link rate requested by the sink
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*
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* Returns true if the requested link rate is supported.
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*/
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static inline bool is_link_rate_valid(u32 bw_code)
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{
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return (bw_code == DP_LINK_BW_1_62 ||
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bw_code == DP_LINK_BW_2_7 ||
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bw_code == DP_LINK_BW_5_4 ||
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bw_code == DP_LINK_BW_8_1);
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}
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/**
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* dp_link_is_lane_count_valid() - validates the lane count
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* @lane_count: lane count requested by the sink
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*
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* Returns true if the requested lane count is supported.
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*/
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static inline bool is_lane_count_valid(u32 lane_count)
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{
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return (lane_count == 1 ||
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lane_count == 2 ||
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lane_count == 4);
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}
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struct dp_panel *dp_panel_get(struct dp_panel_in *in);
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void dp_panel_put(struct dp_panel *dp_panel);
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#endif /* _DP_PANEL_H_ */
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