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b9ec8cbcc2
Other dts have nodes sorted by physical address, be consistent with that. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20200523132223.31108-1-jonathan@marek.ca Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
567 lines
12 KiB
Plaintext
567 lines
12 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-sm8250.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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/ {
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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clocks {
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xo_board: xo-board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <38400000>;
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clock-output-names = "xo_board";
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};
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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#clock-cells = <0>;
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};
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo485";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "cache";
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo485";
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reg = <0x0 0x100>;
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enable-method = "psci";
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next-level-cache = <&L2_100>;
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L2_100: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "qcom,kryo485";
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reg = <0x0 0x200>;
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enable-method = "psci";
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next-level-cache = <&L2_200>;
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L2_200: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "qcom,kryo485";
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reg = <0x0 0x300>;
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enable-method = "psci";
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next-level-cache = <&L2_300>;
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L2_300: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "qcom,kryo485";
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reg = <0x0 0x400>;
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enable-method = "psci";
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next-level-cache = <&L2_400>;
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L2_400: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "qcom,kryo485";
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reg = <0x0 0x500>;
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enable-method = "psci";
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next-level-cache = <&L2_500>;
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L2_500: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "qcom,kryo485";
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reg = <0x0 0x600>;
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enable-method = "psci";
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next-level-cache = <&L2_600>;
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L2_600: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "qcom,kryo485";
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reg = <0x0 0x700>;
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enable-method = "psci";
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next-level-cache = <&L2_700>;
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L2_700: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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};
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firmware {
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scm: scm {
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compatible = "qcom,scm";
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#reset-cells = <1>;
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};
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};
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tcsr_mutex: hwlock {
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compatible = "qcom,tcsr-mutex";
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syscon = <&tcsr_mutex_regs 0 0x1000>;
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#hwlock-cells = <1>;
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};
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memory@80000000 {
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device_type = "memory";
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/* We expect the bootloader to fill in the size */
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reg = <0x0 0x80000000 0x0 0x0>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hyp_mem: memory@80000000 {
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reg = <0x0 0x80000000 0x0 0x600000>;
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no-map;
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};
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xbl_aop_mem: memory@80700000 {
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reg = <0x0 0x80700000 0x0 0x160000>;
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no-map;
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};
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cmd_db: memory@80860000 {
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compatible = "qcom,cmd-db";
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reg = <0x0 0x80860000 0x0 0x20000>;
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no-map;
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};
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smem_mem: memory@80900000 {
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reg = <0x0 0x80900000 0x0 0x200000>;
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no-map;
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};
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removed_mem: memory@80b00000 {
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reg = <0x0 0x80b00000 0x0 0x5300000>;
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no-map;
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};
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camera_mem: memory@86200000 {
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reg = <0x0 0x86200000 0x0 0x500000>;
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no-map;
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};
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wlan_mem: memory@86700000 {
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reg = <0x0 0x86700000 0x0 0x100000>;
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no-map;
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};
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ipa_fw_mem: memory@86800000 {
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reg = <0x0 0x86800000 0x0 0x10000>;
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no-map;
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};
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ipa_gsi_mem: memory@86810000 {
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reg = <0x0 0x86810000 0x0 0xa000>;
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no-map;
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};
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gpu_mem: memory@8681a000 {
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reg = <0x0 0x8681a000 0x0 0x2000>;
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no-map;
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};
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npu_mem: memory@86900000 {
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reg = <0x0 0x86900000 0x0 0x500000>;
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no-map;
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};
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video_mem: memory@86e00000 {
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reg = <0x0 0x86e00000 0x0 0x500000>;
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no-map;
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};
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cvp_mem: memory@87300000 {
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reg = <0x0 0x87300000 0x0 0x500000>;
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no-map;
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};
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cdsp_mem: memory@87800000 {
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reg = <0x0 0x87800000 0x0 0x1400000>;
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no-map;
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};
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slpi_mem: memory@88c00000 {
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reg = <0x0 0x88c00000 0x0 0x1500000>;
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no-map;
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};
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adsp_mem: memory@8a100000 {
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reg = <0x0 0x8a100000 0x0 0x1d00000>;
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no-map;
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};
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spss_mem: memory@8be00000 {
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reg = <0x0 0x8be00000 0x0 0x100000>;
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no-map;
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};
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cdsp_secure_heap: memory@8bf00000 {
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reg = <0x0 0x8bf00000 0x0 0x4600000>;
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no-map;
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};
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};
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smem: qcom,smem {
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compatible = "qcom,smem";
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memory-region = <&smem_mem>;
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hwlocks = <&tcsr_mutex 3>;
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};
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soc: soc@0 {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0 0 0 0 0x10 0>;
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dma-ranges = <0 0 0 0 0x10 0>;
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compatible = "simple-bus";
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gcc: clock-controller@100000 {
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compatible = "qcom,gcc-sm8250";
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reg = <0x0 0x00100000 0x0 0x1f0000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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clock-names = "bi_tcxo", "sleep_clk";
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
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};
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qupv3_id_1: geniqup@ac0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x0 0x00ac0000 0x0 0x6000>;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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uart2: serial@a90000 {
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compatible = "qcom,geni-debug-uart";
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reg = <0x0 0x00a90000 0x0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
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interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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};
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ufs_mem_hc: ufs@1d84000 {
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compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
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"jedec,ufs-2.0";
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reg = <0 0x01d84000 0 0x3000>;
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interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&ufs_mem_phy_lanes>;
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phy-names = "ufsphy";
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lanes-per-direction = <2>;
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#reset-cells = <1>;
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resets = <&gcc GCC_UFS_PHY_BCR>;
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reset-names = "rst";
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power-domains = <&gcc UFS_PHY_GDSC>;
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clock-names =
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"core_clk",
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"bus_aggr_clk",
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"iface_clk",
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"core_clk_unipro",
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"ref_clk",
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"tx_lane0_sync_clk",
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"rx_lane0_sync_clk",
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"rx_lane1_sync_clk";
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clocks =
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<&gcc GCC_UFS_PHY_AXI_CLK>,
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<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
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<&gcc GCC_UFS_PHY_AHB_CLK>,
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<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
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freq-table-hz =
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<37500000 300000000>,
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<0 0>,
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<0 0>,
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<37500000 300000000>,
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<0 0>,
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<0 0>,
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<0 0>,
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<0 0>;
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status = "disabled";
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};
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ufs_mem_phy: phy@1d87000 {
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compatible = "qcom,sm8250-qmp-ufs-phy";
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reg = <0 0x01d87000 0 0x1c0>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clock-names = "ref",
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"ref_aux";
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
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resets = <&ufs_mem_hc 0>;
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reset-names = "ufsphy";
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status = "disabled";
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ufs_mem_phy_lanes: lanes@1d87400 {
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reg = <0 0x01d87400 0 0x108>,
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<0 0x01d87600 0 0x1e0>,
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<0 0x01d87c00 0 0x1dc>,
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<0 0x01d87800 0 0x108>,
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<0 0x01d87a00 0 0x1e0>;
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#phy-cells = <0>;
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};
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};
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tcsr_mutex_regs: syscon@1f40000 {
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compatible = "syscon";
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reg = <0x0 0x01f40000 0x0 0x40000>;
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};
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pdc: interrupt-controller@b220000 {
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compatible = "qcom,sm8250-pdc", "qcom,pdc";
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reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
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qcom,pdc-ranges = <0 480 94>, <94 609 31>,
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<125 63 1>, <126 716 12>;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupt-controller;
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};
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spmi_bus: spmi@c440000 {
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compatible = "qcom,spmi-pmic-arb";
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reg = <0x0 0x0c440000 0x0 0x0001100>,
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<0x0 0x0c600000 0x0 0x2000000>,
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<0x0 0x0e600000 0x0 0x0100000>,
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<0x0 0x0e700000 0x0 0x00a0000>,
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<0x0 0x0c40a000 0x0 0x0026000>;
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reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
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interrupt-names = "periph_irq";
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interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
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qcom,ee = <0>;
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qcom,channel = <0>;
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#address-cells = <2>;
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#size-cells = <0>;
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interrupt-controller;
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#interrupt-cells = <4>;
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};
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intc: interrupt-controller@17a00000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
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<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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timer@17c20000 {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x0 0x17c20000 0x0 0x1000>;
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clock-frequency = <19200000>;
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frame@17c21000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0 0x17c21000 0x0 0x1000>,
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<0x0 0x17c22000 0x0 0x1000>;
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};
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frame@17c23000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0 0x17c23000 0x0 0x1000>;
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status = "disabled";
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};
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frame@17c25000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0 0x17c25000 0x0 0x1000>;
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status = "disabled";
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};
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frame@17c27000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0 0x17c27000 0x0 0x1000>;
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status = "disabled";
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};
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frame@17c29000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0 0x17c29000 0x0 0x1000>;
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status = "disabled";
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};
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frame@17c2b000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0 0x17c2b000 0x0 0x1000>;
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status = "disabled";
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};
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frame@17c2d000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0 0x17c2d000 0x0 0x1000>;
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status = "disabled";
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};
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};
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apps_rsc: rsc@18200000 {
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label = "apps_rsc";
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compatible = "qcom,rpmh-rsc";
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reg = <0x0 0x18200000 0x0 0x10000>,
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<0x0 0x18210000 0x0 0x10000>,
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<0x0 0x18220000 0x0 0x10000>;
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reg-names = "drv-0", "drv-1", "drv-2";
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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qcom,tcs-offset = <0xd00>;
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qcom,drv-id = <2>;
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qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
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<WAKE_TCS 3>, <CONTROL_TCS 1>;
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rpmhcc: clock-controller {
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compatible = "qcom,sm8250-rpmh-clk";
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#clock-cells = <1>;
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clock-names = "xo";
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clocks = <&xo_board>;
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};
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rpmhpd: power-controller {
|
|
compatible = "qcom,sm8250-rpmhpd";
|
|
#power-domain-cells = <1>;
|
|
operating-points-v2 = <&rpmhpd_opp_table>;
|
|
|
|
rpmhpd_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
rpmhpd_opp_ret: opp1 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
|
};
|
|
|
|
rpmhpd_opp_min_svs: opp2 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_low_svs: opp3 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_svs: opp4 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_svs_l1: opp5 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
|
};
|
|
|
|
rpmhpd_opp_nom: opp6 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
|
|
};
|
|
|
|
rpmhpd_opp_nom_l1: opp7 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
|
};
|
|
|
|
rpmhpd_opp_nom_l2: opp8 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
|
|
};
|
|
|
|
rpmhpd_opp_turbo: opp9 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
|
};
|
|
|
|
rpmhpd_opp_turbo_l1: opp10 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13
|
|
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14
|
|
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11
|
|
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 12
|
|
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
};
|