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c00a4cb15a90668684d60bc4ff768a23558dadb9
linux/drivers/gpu/drm/amd/include/asic_reg/gc
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Alex Sierra 4b27a33c3b drm/amdgpu: Force order between a read and write to the same address 
Setting register to force ordering to prevent read/write or write/read
hazards for un-cached modes.

Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.1.x
2023-11-29 17:57:33 -05:00
..
gc_9_0_default.h
drm/amdgpu: remove some old gc 9.x registers
2017-12-13 17:28:08 -05:00
gc_9_0_offset.h
drm/amd/amdgpu: Fix SQ_DEBUG_STS_GLOBAL* registers
2020-07-01 01:59:21 -04:00
gc_9_0_sh_mask.h
drm/amd/amdgpu: Add SQ_DEBUG_STS_GLOBAL* registers/bits
2020-07-01 01:59:19 -04:00
gc_9_1_offset.h
drm/amd/amdgpu: Fix SQ_DEBUG_STS_GLOBAL* registers
2020-07-01 01:59:21 -04:00
gc_9_1_sh_mask.h
drm/amd/amdgpu: Add SQ_DEBUG_STS_GLOBAL* registers/bits
2020-07-01 01:59:19 -04:00
gc_9_2_1_offset.h
drm/amd/amdgpu: Fix SQ_DEBUG_STS_GLOBAL* registers
2020-07-01 01:59:21 -04:00
gc_9_2_1_sh_mask.h
drm/amd/amdgpu: Add SQ_DEBUG_STS_GLOBAL* registers/bits
2020-07-01 01:59:19 -04:00
gc_9_4_1_offset.h
drm/amdgpu: update athub interrupt harvesting handle
2020-09-22 17:37:38 -04:00
gc_9_4_1_sh_mask.h
drm/amdgpu: only harvest gcea/mmea error status in arcturus
2021-04-20 21:35:45 -04:00
gc_9_4_2_offset.h
drm/amd/amdgpu: add regCP_MEx_INT_STAT_DEBUG for Aldebaran debugging
2021-08-05 21:17:59 -04:00
gc_9_4_2_sh_mask.h
drm/amd/amdgpu: add regCP_MEx_INT_STAT_DEBUG for Aldebaran debugging
2021-08-05 21:17:59 -04:00
gc_9_4_3_offset.h
drm/amdgpu: Add gc v9_4_3 ras error status registers
2023-06-09 10:37:34 -04:00
gc_9_4_3_sh_mask.h
drm/amdgpu: Add gc v9_4_3 ras error status registers
2023-06-09 10:37:34 -04:00
gc_10_1_0_default.h
drm/amdgpu: add GC 10.1 register headers (v4)
2019-06-20 15:54:35 -05:00
gc_10_1_0_offset.h
drm/amdgpu: setup hw debug registers on driver initialization
2023-06-09 12:34:56 -04:00
gc_10_1_0_sh_mask.h
drm/amdgpu: setup hw debug registers on driver initialization
2023-06-09 12:34:56 -04:00
gc_10_3_0_default.h
drm/amdgpu: add GC 10.3 NOALLOC registers
2020-10-23 15:33:47 -04:00
gc_10_3_0_offset.h
drm/amdgpu: setup hw debug registers on driver initialization
2023-06-09 12:34:56 -04:00
gc_10_3_0_sh_mask.h
drm/amdgpu: setup hw debug registers on driver initialization
2023-06-09 12:34:56 -04:00
gc_11_0_0_default.h
drm/amdgpu: add gc v11_0_0 ip headers v11
2022-04-28 17:48:28 -04:00
gc_11_0_0_offset.h
drm/amdgpu: Force order between a read and write to the same address
2023-11-29 17:57:33 -05:00
gc_11_0_0_sh_mask.h
drm/amdgpu: setup hw debug registers on driver initialization
2023-06-09 12:34:56 -04:00
gc_11_0_3_offset.h
amd/amdgpu: Add RLC_RLCS_FED_STATUS_* to gc v11_0_3 ip headers
2023-01-17 16:11:50 -05:00
gc_11_0_3_sh_mask.h
amd/amdgpu: Add RLC_RLCS_FED_STATUS_* to gc v11_0_3 ip headers
2023-01-17 16:11:50 -05:00
gc_11_5_0_offset.h
drm/amdgpu: add gc headers for gc 11.5.0
2023-08-30 15:00:34 -04:00
gc_11_5_0_sh_mask.h
drm/amdgpu: update to the latest GC 11.5 headers
2023-10-19 18:26:51 -04:00