Mathias Kresin 5b042d2f8b MIPS: ath79: Fix AR724X_PLL_REG_PCIE_CONFIG offset ...

[ Upstream commit 05454c1bde ]

According to the QCA u-boot source the "PCIE Phase Lock Loop
Configuration (PCIE_PLL_CONFIG)" register is for all SoCs except the
QCA955X and QCA956X at offset 0x10.

Since the PCIE PLL config register is only defined for the AR724x fix
only this value. The value is wrong since the day it was added and isn't
used by any driver yet.

Signed-off-by: Mathias Kresin <dev@kresin.me>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16048/
Signed-off-by: James Hogan <jhogan@kernel.org>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

2018-05-30 08:17:34 +02:00

..

asm

MIPS: ath79: Fix AR724X_PLL_REG_PCIE_CONFIG offset

2018-05-30 08:17:34 +02:00

uapi/asm

unify {de,}mangle_poll(), get rid of kernel-side POLL...

2018-02-11 14:37:22 -08:00