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Jerome Brunet 3ede9f3e4b clk: meson: axg: add the fractional part of the fixed_pll

[ Upstream commit 6b71aceceb ]

The fixed_pll also has a fractional part. On axg s400 board, without
this parameter, the calculated rate is off by ~8Mhz (0,4%). The fixed_pll
being the root of the peripheral clock tree, this error is propagated to
the rest of the clocks

Adding the definition of the parameter fixes the problem

Fixes: 78b4af312f ("clk: meson-axg: add clock controller drivers")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

2018-05-25 16:46:17 +02:00

axg.c

clk: meson: axg: add the fractional part of the fixed_pll

2018-05-25 16:46:17 +02:00

axg.h

clk: meson-axg: add clock controller drivers

2017-12-14 10:19:37 +01:00

clk-audio-divider.c

clk: meson: add audio clock divider support

2017-04-07 16:50:44 +02:00

clk-cpu.c

clk: meson8b: clean up cpu clocks