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61d0301e6c
Add the missing size and address cells to the b53 example. Otherwise, it may not compile or issue warnings if directly copied into a device tree. Signed-off-by: Kurt Kanzenbach <kurt@linutronix.de> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
149 lines
3.6 KiB
Plaintext
149 lines
3.6 KiB
Plaintext
Broadcom BCM53xx Ethernet switches
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==================================
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Required properties:
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- compatible: For external switch chips, compatible string must be exactly one
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of: "brcm,bcm5325"
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"brcm,bcm53115"
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"brcm,bcm53125"
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"brcm,bcm53128"
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"brcm,bcm5365"
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"brcm,bcm5395"
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"brcm,bcm5389"
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"brcm,bcm5397"
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"brcm,bcm5398"
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For the BCM11360 SoC, must be:
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"brcm,bcm11360-srab" and the mandatory "brcm,cygnus-srab" string
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For the BCM5310x SoCs with an integrated switch, must be one of:
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"brcm,bcm53010-srab"
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"brcm,bcm53011-srab"
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"brcm,bcm53012-srab"
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"brcm,bcm53018-srab"
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"brcm,bcm53019-srab" and the mandatory "brcm,bcm5301x-srab" string
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For the BCM5831X/BCM1140x SoCs with an integrated switch, must be one of:
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"brcm,bcm11404-srab"
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"brcm,bcm11407-srab"
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"brcm,bcm11409-srab"
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"brcm,bcm58310-srab"
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"brcm,bcm58311-srab"
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"brcm,bcm58313-srab" and the mandatory "brcm,omega-srab" string
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For the BCM585xx/586XX/88312 SoCs with an integrated switch, must be one of:
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"brcm,bcm58522-srab"
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"brcm,bcm58523-srab"
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"brcm,bcm58525-srab"
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"brcm,bcm58622-srab"
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"brcm,bcm58623-srab"
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"brcm,bcm58625-srab"
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"brcm,bcm88312-srab" and the mandatory "brcm,nsp-srab string
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For the BCM63xx/33xx SoCs with an integrated switch, must be one of:
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"brcm,bcm3384-switch"
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"brcm,bcm6328-switch"
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"brcm,bcm6368-switch" and the mandatory "brcm,bcm63xx-switch"
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Required properties for BCM585xx/586xx/88312 SoCs:
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- reg: a total of 3 register base addresses, the first one must be the
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Switch Register Access block base, the second is the port 5/4 mux
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configuration register and the third one is the SGMII configuration
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and status register base address.
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- interrupts: a total of 13 interrupts must be specified, in the following
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order: port 0-5, 7-8 link status change, then the integrated PHY interrupt,
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then the timestamping interrupt and the sleep timer interrupts for ports
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5,7,8.
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Optional properties for BCM585xx/586xx/88312 SoCs:
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- reg-names: a total of 3 names matching the 3 base register address, must
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be in the following order:
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"srab"
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"mux_config"
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"sgmii_config"
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- interrupt-names: a total of 13 names matching the 13 interrupts specified
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must be in the following order:
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"link_state_p0"
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"link_state_p1"
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"link_state_p2"
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"link_state_p3"
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"link_state_p4"
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"link_state_p5"
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"link_state_p7"
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"link_state_p8"
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"phy"
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"ts"
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"imp_sleep_timer_p5"
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"imp_sleep_timer_p7"
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"imp_sleep_timer_p8"
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See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional
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required and optional properties.
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Examples:
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Ethernet switch connected via MDIO to the host, CPU port wired to eth0:
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eth0: ethernet@10001000 {
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compatible = "brcm,unimac";
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reg = <0x10001000 0x1000>;
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fixed-link {
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speed = <1000>;
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duplex-full;
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};
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};
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mdio0: mdio@10000000 {
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compatible = "brcm,unimac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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switch0: ethernet-switch@30 {
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compatible = "brcm,bcm53125";
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port0@0 {
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reg = <0>;
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label = "lan1";
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};
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port1@1 {
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reg = <1>;
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label = "lan2";
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};
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port5@5 {
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reg = <5>;
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label = "cable-modem";
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fixed-link {
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speed = <1000>;
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duplex-full;
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};
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phy-mode = "rgmii-txid";
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};
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port8@8 {
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reg = <8>;
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label = "cpu";
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fixed-link {
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speed = <1000>;
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duplex-full;
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};
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phy-mode = "rgmii-txid";
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ethernet = <ð0>;
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};
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};
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};
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};
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