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d27cb32e00eff60d8fa94de265a8d84c63ef059c
linux/drivers/clk/renesas
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Claudiu Beznea 4bce4bedbe clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2 
Add clock and reset support for the SDHI1 and SDHI2 blocks on the
RZ/G3S (R9A08G045) SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231010132701.1658737-3-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-10-12 20:05:52 +02:00
..
clk-div6.c
clk: renesas: div6: Implement range checking
2021-05-11 09:58:13 +02:00
clk-div6.h
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
2017-11-17 20:04:24 -08:00
clk-emev2.c
clk: renesas: emev2: Remove obsolete clkdev registration
2023-07-27 14:32:41 +02:00
clk-mstp.c
clk: renesas: mstp: Convert to readl_poll_timeout_atomic()
2023-06-05 15:41:43 +02:00
clk-r8a73a4.c
clk: renesas: r8a73a4: Remove r8a73a4_cpg.reg
2022-06-13 11:53:18 +02:00
clk-r8a7740.c
clk: renesas: r8a7740: Remove r8a7740_cpg.reg
2022-06-13 11:53:18 +02:00
clk-r8a7778.c
clk: renesas: r8a7778: Remove struct r8a7778_cpg
2022-06-13 11:53:18 +02:00
clk-r8a7779.c
clk: renesas: r8a7779: Remove struct r8a7779_cpg
2022-06-13 11:53:18 +02:00
clk-rz.c
clk: renesas: rza1: Remove struct rz_cpg
2022-06-13 11:53:18 +02:00
clk-sh73a0.c
clk: renesas: sh73a0: Remove sh73a0_cpg.reg
2022-06-13 11:53:18 +02:00
Kconfig
clk: renesas: Add minimal boot support for RZ/G3S SoC
2023-10-10 09:29:48 +02:00
Makefile
clk: renesas: Add minimal boot support for RZ/G3S SoC
2023-10-10 09:29:48 +02:00
r7s9210-cpg-mssr.c
clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag
2020-09-17 15:30:08 +02:00
r8a774a1-cpg-mssr.c
clk: renesas: rcar-gen3: Add ADG clocks
2023-08-15 11:34:43 +02:00
r8a774b1-cpg-mssr.c
clk: renesas: rcar-gen3: Add ADG clocks
2023-08-15 11:34:43 +02:00
r8a774c0-cpg-mssr.c
clk: renesas: rcar-gen3: Add ADG clocks
2023-08-15 11:34:43 +02:00
r8a774e1-cpg-mssr.c
clk: renesas: rcar-gen3: Add ADG clocks
2023-08-15 11:34:43 +02:00
r8a779a0-cpg-mssr.c
clk: renesas: r8a779a0: Add PWM clock
2023-05-08 09:14:33 +02:00
r8a779f0-cpg-mssr.c
clk: renesas: r8a779f0: Fix Ethernet Switch clocks
2022-11-16 09:05:59 +01:00
r8a779g0-cpg-mssr.c
clk: renesas: r8a779g0: Add VIN clocks
2023-03-06 10:42:14 +01:00
r8a7742-cpg-mssr.c
clk: renesas: r8a7742: Add clk entry for VSPR
2020-09-04 09:42:01 +02:00
r8a7743-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7745-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7790-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7791-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7792-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7794-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7795-cpg-mssr.c
clk: renesas: r8a7795: Constify r8a7795_*_clks
2023-09-26 09:38:00 +02:00
r8a7796-cpg-mssr.c
clk: renesas: rcar-gen3: Add ADG clocks
2023-08-15 11:34:43 +02:00
r8a77470-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a77965-cpg-mssr.c
clk: renesas: rcar-gen3: Add ADG clocks
2023-08-15 11:34:43 +02:00
r8a77970-cpg-mssr.c
clk: renesas: r8a77970: Add Z2 clock
2023-03-10 17:07:07 +01:00
r8a77980-cpg-mssr.c
clk: renesas: r8a77980: Add I2C5 clock
2023-03-30 16:44:04 +02:00
r8a77990-cpg-mssr.c
clk: renesas: rcar-gen3: Add ADG clocks
2023-08-15 11:34:43 +02:00
r8a77995-cpg-mssr.c
clk: renesas: rcar-gen3: Add ADG clocks
2023-08-15 11:34:43 +02:00
r9a06g032-clocks.c
clk: renesas: r9a06g032: Name anonymous structs
2023-09-18 10:05:23 +02:00
r9a07g043-cpg.c
clk: renesas: rzg2l: Refactor SD mux driver
2023-10-10 09:16:11 +02:00
r9a07g044-cpg.c
clk: renesas: rzg2l: Refactor SD mux driver
2023-10-10 09:16:11 +02:00
r9a08g045-cpg.c
clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2
2023-10-12 20:05:52 +02:00
r9a09g011-cpg.c
clk: renesas: r9a09g011: Add CSI related clocks
2023-07-10 09:31:53 +02:00
rcar-cpg-lib.c
clk: renesas: rcar-gen3: Extend SDnH divider table
2023-10-05 13:44:34 +02:00
rcar-cpg-lib.h
clk: renesas: rcar-gen3: Switch to new SD clock handling
2021-11-19 11:32:39 +01:00
rcar-gen2-cpg.c
clk: renesas: Zero init clk_init_data
2021-03-30 09:58:27 +02:00
rcar-gen2-cpg.h
clk: renesas: rcar-gen2: Change multipliers and dividers to u8
2019-12-10 10:24:10 +01:00
rcar-gen3-cpg.c
clk: renesas: rcar-gen3: Add support for ZG clock
2023-07-10 09:31:29 +02:00
rcar-gen3-cpg.h
clk: renesas: rcar-gen3: Add support for ZG clock
2023-07-10 09:31:29 +02:00
rcar-gen4-cpg.c
clk: renesas: r8a779g0: Add custom clock for PLL2
2023-01-24 10:11:50 +01:00
rcar-gen4-cpg.h
clk: renesas: r8a779g0: Add custom clock for PLL2
2023-01-24 10:11:50 +01:00
rcar-usb2-clock-sel.c
clk: Explicitly include correct DT includes
2023-07-19 13:13:16 -07:00
renesas-cpg-mssr.c
clk: Explicitly include correct DT includes
2023-07-19 13:13:16 -07:00
renesas-cpg-mssr.h
clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*
2023-02-10 10:35:16 +01:00
rzg2l-cpg.c
clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R()
2023-10-12 20:05:36 +02:00
rzg2l-cpg.h
clk: renesas: Add minimal boot support for RZ/G3S SoC
2023-10-10 09:29:48 +02:00