mirror of
https://github.com/raspberrypi/linux.git
synced 2025-12-07 02:19:54 +00:00
Pull pci updates from Bjorn Helgaas:
"Enumeration:
- Wait for device readiness after reset by polling Vendor ID and
looking for Configuration RRS instead of polling the Command
register and looking for non-error completions, to avoid hardware
retries done for RRS on non-Vendor ID reads (Bjorn Helgaas)
- Rename CRS Completion Status to RRS ('Request Retry Status') to
match PCIe r6.0 spec usage (Bjorn Helgaas)
- Clear LBMS bit after a manual link retrain so we don't try to
retrain a link when there's no downstream device anymore (Maciej W.
Rozycki)
- Revert to the original link speed after retraining fails instead of
leaving it restricted to 2.5GT/s, so a future device has a chance
to use higher speeds (Maciej W. Rozycki)
- Wait for each level of downstream bus, not just the first, to
become accessible before restoring devices on that bus (Ilpo
Järvinen)
- Add ARCH_PCI_DEV_GROUPS so s390 can add its own attribute_groups
without having to stomp on the core's pdev->dev.groups (Lukas
Wunner)
Driver binding:
- Export pcim_request_region(), a managed counterpart of
pci_request_region(), for use by drivers (Philipp Stanner)
- Export pcim_iomap_region() and deprecate pcim_iomap_regions()
(Philipp Stanner)
- Request the PCI BAR used by xboxvideo (Philipp Stanner)
- Request and map drm/ast BARs with pcim_iomap_region() (Philipp
Stanner)
MSI:
- Add MSI_FLAG_NO_AFFINITY flag for devices that mux MSIs onto a
single IRQ line and cannot set the affinity of each MSI to a
specific CPU core (Marek Vasut)
- Use MSI_FLAG_NO_AFFINITY and remove unnecessary .irq_set_affinity()
implementations in aardvark, altera, brcmstb, dwc, mediatek-gen3,
mediatek, mobiveil, plda, rcar, tegra, vmd, xilinx-nwl,
xilinx-xdma, and xilinx drivers to avoid 'IRQ: set affinity failed'
warnings (Marek Vasut)
Power management:
- Add pwrctl support for ATH11K inside the WCN6855 package (Konrad
Dybcio)
PCI device hotplug:
- Remove unnecessary hpc_ops struct from shpchp (ngn)
- Check for PCI_POSSIBLE_ERROR(), not 0xffffffff, in cpqphp
(weiyufeng)
Virtualization:
- Mark Creative Labs EMU20k2 INTx masking as broken (Alex Williamson)
- Add an ACS quirk for Qualcomm SA8775P, which doesn't advertise ACS
but does provide ACS-like features (Subramanian Ananthanarayanan)
IOMMU:
- Add function 0 DMA alias quirk for Glenfly Arise audio function,
which uses the function 0 Requester ID (WangYuli)
NPEM:
- Add Native PCIe Enclosure Management (NPEM) support for sysfs
control of NVMe RAID storage indicators (ok/fail/locate/
rebuild/etc) (Mariusz Tkaczyk)
- Add support for the ACPI _DSM PCIe SSD status LED management, which
is functionally similar to NPEM but mediated by platform firmware
(Mariusz Tkaczyk)
Device trees:
- Drop minItems and maxItems from ranges in PCI generic host binding
since host bridges may have several MMIO and I/O port apertures
(Frank Li)
- Add kirin, rcar-gen2, uniphier DT binding top-level constraints for
clocks (Krzysztof Kozlowski)
Altera PCIe controller driver:
- Convert altera DT bindings from text to YAML (Matthew Gerlach)
- Replace TLP_REQ_ID() with macro PCI_DEVID(), which does the same
thing and is what other drivers use (Jinjie Ruan)
Broadcom STB PCIe controller driver:
- Add DT binding maxItems for reset controllers (Jim Quinlan)
- Use the 'bridge' reset method if described in the DT (Jim Quinlan)
- Use the 'swinit' reset method if described in the DT (Jim Quinlan)
- Add 'has_phy' so the existence of a 'rescal' reset controller
doesn't imply software control of it (Jim Quinlan)
- Add support for many inbound DMA windows (Jim Quinlan)
- Rename SoC 'type' to 'soc_base' express the fact that SoCs come in
families of multiple similar devices (Jim Quinlan)
- Add Broadcom 7712 DT description and driver support (Jim Quinlan)
- Sort enums, pcie_offsets[], pcie_cfg_data, .compatible strings for
maintainability (Bjorn Helgaas)
Freescale i.MX6 PCIe controller driver:
- Add imx6q-pcie 'dbi2' and 'atu' reg-names for i.MX8M Endpoints
(Richard Zhu)
- Fix a code restructuring error that caused i.MX8MM and i.MX8MP
Endpoints to fail to establish link (Richard Zhu)
- Fix i.MX8MP Endpoint occasional failure to trigger MSI by enforcing
outbound alignment requirement (Richard Zhu)
- Call phy_power_off() in the .probe() error path (Frank Li)
- Rename internal names from imx6_* to imx_* since i.MX7/8/9 are also
supported (Frank Li)
- Manage Refclk by using SoC-specific callbacks instead of switch
statements (Frank Li)
- Manage core reset by using SoC-specific callbacks instead of switch
statements (Frank Li)
- Expand comments for erratum ERR010728 workaround (Frank Li)
- Use generic PHY APIs to configure mode, speed, and submode, which
is harmless for devices that implement their own internal PHY
management and don't set the generic imx_pcie->phy (Frank Li)
- Add i.MX8Q (i.MX8QM, i.MX8QXP, and i.MX8DXL) DT binding and driver
Root Complex support (Richard Zhu)
Freescale Layerscape PCIe controller driver:
- Replace layerscape-pcie DT binding compatible fsl,lx2160a-pcie with
fsl,lx2160ar2-pcie (Frank Li)
- Add layerscape-pcie DT binding deprecated 'num-viewport' property
to address a DT checker warning (Frank Li)
- Change layerscape-pcie DT binding 'fsl,pcie-scfg' to phandle-array
(Frank Li)
Loongson PCIe controller driver:
- Increase max PCI hosts to 8 for Loongson-3C6000 and newer chipsets
(Huacai Chen)
Marvell Aardvark PCIe controller driver:
- Fix issue with emulating Configuration RRS for two-byte reads of
Vendor ID; previously it only worked for four-byte reads (Bjorn
Helgaas)
MediaTek PCIe Gen3 controller driver:
- Add per-SoC struct mtk_gen3_pcie_pdata to support multiple SoC
types (Lorenzo Bianconi)
- Use reset_bulk APIs to manage PHY reset lines (Lorenzo Bianconi)
- Add DT and driver support for Airoha EN7581 PCIe controller
(Lorenzo Bianconi)
Qualcomm PCIe controller driver:
- Update qcom,pcie-sc7280 DT binding with eight interrupts (Rayyan
Ansari)
- Add back DT 'vddpe-3v3-supply', which was incorrectly removed
earlier (Johan Hovold)
- Drop endpoint redundant masking of global IRQ events (Manivannan
Sadhasivam)
- Clarify unknown global IRQ message and only log it once to avoid a
flood (Manivannan Sadhasivam)
- Add 'linux,pci-domain' property to endpoint DT binding (Manivannan
Sadhasivam)
- Assign PCI domain number for endpoint controllers (Manivannan
Sadhasivam)
- Add 'qcom_pcie_ep' and the PCI domain number to IRQ names for
endpoint controller (Manivannan Sadhasivam)
- Add global SPI interrupt for PCIe link events to DT binding
(Manivannan Sadhasivam)
- Add global RC interrupt handler to handle 'Link up' events and
automatically enumerate hot-added devices (Manivannan Sadhasivam)
- Avoid mirroring of DBI and iATU register space so it doesn't
overlap BAR MMIO space (Prudhvi Yarlagadda)
- Enable controller resources like PHY only after PERST# is
deasserted to partially avoid the problem that the endpoint SoC
crashes when accessing things when Refclk is absent (Manivannan
Sadhasivam)
- Add 16.0 GT/s equalization and RX lane margining settings (Shashank
Babu Chinta Venkata)
- Pass domain number to pci_bus_release_domain_nr() explicitly to
avoid a NULL pointer dereference (Manivannan Sadhasivam)
Renesas R-Car PCIe controller driver:
- Make the read-only const array 'check_addr' static (Colin Ian King)
- Add R-Car V4M (R8A779H0) PCIe host and endpoint to DT binding
(Yoshihiro Shimoda)
TI DRA7xx PCIe controller driver:
- Request IRQF_ONESHOT for 'dra7xx-pcie-main' IRQ since the primary
handler is NULL (Siddharth Vadapalli)
- Handle IRQ request errors during root port and endpoint probe
(Siddharth Vadapalli)
TI J721E PCIe driver:
- Add DT 'ti,syscon-acspcie-proxy-ctrl' and driver support to enable
the ACSPCIE module to drive Refclk for the Endpoint (Siddharth
Vadapalli)
- Extract the cadence link setup from cdns_pcie_host_setup() so link
setup can be done separately during resume (Thomas Richard)
- Add T_PERST_CLK_US definition for the mandatory delay between
Refclk becoming stable and PERST# being deasserted (Thomas Richard)
- Add j721e suspend and resume support (Théo Lebrun)
TI Keystone PCIe controller driver:
- Fix NULL pointer checking when applying MRRS limitation quirk for
AM65x SR 1.0 Errata #i2037 (Dan Carpenter)
Xilinx NWL PCIe controller driver:
- Fix off-by-one error in INTx IRQ handler that caused INTx
interrupts to be lost or delivered as the wrong interrupt (Sean
Anderson)
- Rate-limit misc interrupt messages (Sean Anderson)
- Turn off the clock on probe failure and device removal (Sean
Anderson)
- Add DT binding and driver support for enabling/disabling PHYs (Sean
Anderson)
- Add PCIe phy bindings for the ZCU102 (Sean Anderson)
Xilinx XDMA PCIe controller driver:
- Add support for Xilinx QDMA Soft IP PCIe Root Port Bridge to DT
binding and xilinx-dma-pl driver (Thippeswamy Havalige)
Miscellaneous:
- Fix buffer overflow in kirin_pcie_parse_port() (Alexandra Diupina)
- Fix minor kerneldoc issues and typos (Bjorn Helgaas)
- Use PCI_DEVID() macro in aer_inject() instead of open-coding it
(Jinjie Ruan)
- Check pcie_find_root_port() return in x86 fixups to avoid NULL
pointer dereferences (Samasth Norway Ananda)
- Make pci_bus_type constant (Kunwu Chan)
- Remove unused declarations of __pci_pme_wakeup() and
pci_vpd_release() (Yue Haibing)
- Remove any leftover .*.cmd files with make clean (zhang jiao)
- Remove unused BILLION macro (zhang jiao)"
* tag 'pci-v6.12-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (132 commits)
PCI: Fix typos
dt-bindings: PCI: qcom: Allow 'vddpe-3v3-supply' again
tools: PCI: Remove unused BILLION macro
tools: PCI: Remove .*.cmd files with make clean
PCI: Pass domain number to pci_bus_release_domain_nr() explicitly
PCI: dra7xx: Fix error handling when IRQ request fails in probe
PCI: dra7xx: Fix threaded IRQ request for "dra7xx-pcie-main" IRQ
PCI: qcom: Add RX lane margining settings for 16.0 GT/s
PCI: qcom: Add equalization settings for 16.0 GT/s
PCI: dwc: Always cache the maximum link speed value in dw_pcie::max_link_speed
PCI: dwc: Rename 'dw_pcie::link_gen' to 'dw_pcie::max_link_speed'
PCI: qcom-ep: Enable controller resources like PHY only after refclk is available
PCI: Mark Creative Labs EMU20k2 INTx masking as broken
dt-bindings: PCI: imx6q-pcie: Add reg-name "dbi2" and "atu" for i.MX8M PCIe Endpoint
dt-bindings: PCI: altera: msi: Convert to YAML
PCI: imx6: Add i.MX8Q PCIe Root Complex (RC) support
PCI: Rename CRS Completion Status to RRS
PCI: aardvark: Correct Configuration RRS checking
PCI: Wait for device readiness with Configuration RRS
PCI: brcmstb: Sort enums, pcie_offsets[], pcie_cfg_data, .compatible strings
...
194 lines
4.4 KiB
C
194 lines
4.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/pci.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include "pci.h"
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static void pci_free_resources(struct pci_dev *dev)
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{
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struct resource *res;
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pci_dev_for_each_resource(dev, res) {
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if (res->parent)
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release_resource(res);
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}
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}
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static int pci_pwrctl_unregister(struct device *dev, void *data)
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{
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struct device_node *pci_node = data, *plat_node = dev_of_node(dev);
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if (dev_is_platform(dev) && plat_node && plat_node == pci_node) {
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of_device_unregister(to_platform_device(dev));
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of_node_clear_flag(plat_node, OF_POPULATED);
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}
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return 0;
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}
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static void pci_stop_dev(struct pci_dev *dev)
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{
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pci_pme_active(dev, false);
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if (pci_dev_is_added(dev)) {
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device_for_each_child(dev->dev.parent, dev_of_node(&dev->dev),
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pci_pwrctl_unregister);
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device_release_driver(&dev->dev);
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pci_proc_detach_device(dev);
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pci_remove_sysfs_dev_files(dev);
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of_pci_remove_node(dev);
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pci_dev_assign_added(dev, false);
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}
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}
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static void pci_destroy_dev(struct pci_dev *dev)
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{
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if (!dev->dev.kobj.parent)
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return;
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pci_npem_remove(dev);
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device_del(&dev->dev);
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down_write(&pci_bus_sem);
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list_del(&dev->bus_list);
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up_write(&pci_bus_sem);
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pci_doe_destroy(dev);
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pcie_aspm_exit_link_state(dev);
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pci_bridge_d3_update(dev);
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pci_free_resources(dev);
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put_device(&dev->dev);
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}
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void pci_remove_bus(struct pci_bus *bus)
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{
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pci_proc_detach_bus(bus);
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down_write(&pci_bus_sem);
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list_del(&bus->node);
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pci_bus_release_busn_res(bus);
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up_write(&pci_bus_sem);
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pci_remove_legacy_files(bus);
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if (bus->ops->remove_bus)
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bus->ops->remove_bus(bus);
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pcibios_remove_bus(bus);
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device_unregister(&bus->dev);
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}
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EXPORT_SYMBOL(pci_remove_bus);
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static void pci_stop_bus_device(struct pci_dev *dev)
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{
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struct pci_bus *bus = dev->subordinate;
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struct pci_dev *child, *tmp;
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/*
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* Stopping an SR-IOV PF device removes all the associated VFs,
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* which will update the bus->devices list and confuse the
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* iterator. Therefore, iterate in reverse so we remove the VFs
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* first, then the PF.
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*/
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if (bus) {
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list_for_each_entry_safe_reverse(child, tmp,
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&bus->devices, bus_list)
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pci_stop_bus_device(child);
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}
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pci_stop_dev(dev);
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}
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static void pci_remove_bus_device(struct pci_dev *dev)
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{
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struct pci_bus *bus = dev->subordinate;
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struct pci_dev *child, *tmp;
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if (bus) {
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list_for_each_entry_safe(child, tmp,
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&bus->devices, bus_list)
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pci_remove_bus_device(child);
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pci_remove_bus(bus);
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dev->subordinate = NULL;
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}
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pci_destroy_dev(dev);
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}
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/**
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* pci_stop_and_remove_bus_device - remove a PCI device and any children
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* @dev: the device to remove
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*
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* Remove a PCI device from the device lists, informing the drivers
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* that the device has been removed. We also remove any subordinate
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* buses and children in a depth-first manner.
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*
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* For each device we remove, delete the device structure from the
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* device lists, remove the /proc entry, and notify userspace
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* (/sbin/hotplug).
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*/
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void pci_stop_and_remove_bus_device(struct pci_dev *dev)
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{
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pci_stop_bus_device(dev);
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pci_remove_bus_device(dev);
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}
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EXPORT_SYMBOL(pci_stop_and_remove_bus_device);
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void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev)
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{
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pci_lock_rescan_remove();
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pci_stop_and_remove_bus_device(dev);
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pci_unlock_rescan_remove();
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}
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EXPORT_SYMBOL_GPL(pci_stop_and_remove_bus_device_locked);
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void pci_stop_root_bus(struct pci_bus *bus)
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{
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struct pci_dev *child, *tmp;
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struct pci_host_bridge *host_bridge;
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if (!pci_is_root_bus(bus))
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return;
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host_bridge = to_pci_host_bridge(bus->bridge);
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list_for_each_entry_safe_reverse(child, tmp,
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&bus->devices, bus_list)
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pci_stop_bus_device(child);
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/* stop the host bridge */
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device_release_driver(&host_bridge->dev);
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}
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EXPORT_SYMBOL_GPL(pci_stop_root_bus);
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void pci_remove_root_bus(struct pci_bus *bus)
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{
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struct pci_dev *child, *tmp;
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struct pci_host_bridge *host_bridge;
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if (!pci_is_root_bus(bus))
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return;
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host_bridge = to_pci_host_bridge(bus->bridge);
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list_for_each_entry_safe(child, tmp,
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&bus->devices, bus_list)
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pci_remove_bus_device(child);
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#ifdef CONFIG_PCI_DOMAINS_GENERIC
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/* Release domain_nr if it was dynamically allocated */
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if (host_bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET)
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pci_bus_release_domain_nr(host_bridge->dev.parent, bus->domain_nr);
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#endif
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pci_remove_bus(bus);
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host_bridge->bus = NULL;
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/* remove the host bridge */
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device_del(&host_bridge->dev);
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}
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EXPORT_SYMBOL_GPL(pci_remove_root_bus);
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