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d7378f84e9
Introduce a core state management for iris driver with the necessary
queues needed for the host firmware communication.
There are 3 types of queues:
Command queue - driver to write any command to firmware.
Message queue - firmware to send any response to the driver.
Debug queue - for the firmware to write debug messages.
Initialize and configure the shared queues during probe.
Different states for core:
IRIS_CORE_DEINIT - default state.
IRIS_CORE_INIT - core state with core initialized. FW loaded and HW
brought out of reset, shared queues established
between host driver and firmware.
IRIS_CORE_ERROR - error state.
-----------
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V
-----------
| DEINIT |
-----------
^
/ \
/ \
/ \
/ \
v v
----------- ----------.
| INIT |-->| ERROR |
----------- ----------.
Tested-by: Stefan Schmidt <stefan.schmidt@linaro.org> # x1e80100 (Dell XPS 13 9345)
Reviewed-by: Stefan Schmidt <stefan.schmidt@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
Signed-off-by: Dikshita Agarwal <quic_dikshita@quicinc.com>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
178 lines
6.0 KiB
C
178 lines
6.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef __IRIS_HFI_QUEUE_H__
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#define __IRIS_HFI_QUEUE_H__
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struct iris_core;
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/*
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* Max 64 Buffers ( 32 input buffers and 32 output buffers)
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* can be queued by v4l2 framework at any given time.
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*/
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#define IFACEQ_MAX_BUF_COUNT 64
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/*
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* Max session supported are 16.
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* this value is used to calcualte the size of
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* individual shared queue.
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*/
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#define IFACE_MAX_PARALLEL_SESSIONS 16
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#define IFACEQ_DFLT_QHDR 0x0101
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#define IFACEQ_MAX_PKT_SIZE 1024 /* Maximum size of a packet in the queue */
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/*
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* SFR: Subsystem Failure Reason
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* when hardware goes into bad state/failure, firmware fills this memory
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* and driver will get to know the actual failure reason from this SFR buffer.
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*/
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#define SFR_SIZE SZ_4K /* Iris hardware requires 4K queue alignment */
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#define IFACEQ_QUEUE_SIZE (IFACEQ_MAX_PKT_SIZE * \
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IFACEQ_MAX_BUF_COUNT * IFACE_MAX_PARALLEL_SESSIONS)
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/*
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* Memory layout of the shared queues:
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*
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* ||=================|| ^ ^ ^
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* || || | | |
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* || Queue Table || 288 Bytes | |
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* || Header || | | |
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* || || | | |
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* ||-----------------|| V | |
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* ||-----------------|| ^ | |
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* || || | | |
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* || Command Queue || 56 Bytes | |
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* || Header || | | |
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* || || | | |
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* ||-----------------|| V 456 Bytes |
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* ||-----------------|| ^ | |
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* || || | | |
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* || Message Queue || 56 Bytes | |
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* || Header || | | |
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* || || | | |
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* ||-----------------|| V | Buffer size aligned to 4k
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* ||-----------------|| ^ | Overall Queue Size = 2,404 KB
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* || || | | |
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* || Debug Queue || 56 Bytes | |
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* || Header || | | |
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* || || | | |
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* ||=================|| V V |
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* ||=================|| ^ |
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* || || | |
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* || Command || 800 KB |
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* || Queue || | |
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* || || | |
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* ||=================|| V |
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* ||=================|| ^ |
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* || || | |
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* || Message || 800 KB |
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* || Queue || | |
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* || || | |
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* ||=================|| V |
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* ||=================|| ^ |
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* || || | |
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* || Debug || 800 KB |
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* || Queue || | |
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* || || | |
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* ||=================|| V |
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* || || |
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* ||=================|| V
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*/
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/*
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* Shared queues are used for communication between driver and firmware.
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* There are 3 types of queues:
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* Command queue - driver to write any command to firmware.
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* Message queue - firmware to send any response to driver.
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* Debug queue - firmware to write debug message.
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*/
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/* Host-firmware shared queue ids */
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enum iris_iface_queue {
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IFACEQ_CMDQ_ID,
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IFACEQ_MSGQ_ID,
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IFACEQ_DBGQ_ID,
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IFACEQ_NUMQ, /* not an index */
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};
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/**
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* struct iris_hfi_queue_header
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*
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* @status: Queue status, bits (7:0), 0x1 - active, 0x0 - inactive
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* @start_addr: Queue start address in non cached memory
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* @queue_type: Queue ID
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* @header_type: Default queue header
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* @q_size: Queue size
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* Number of queue packets if pkt_size is non-zero
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* Queue size in bytes if pkt_size is zero
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* @pkt_size: Size of queue packet entries
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* 0x0: variable queue packet size
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* non zero: size of queue packet entry, fixed
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* @pkt_drop_cnt: Number of packets dropped by sender
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* @rx_wm: Receiver watermark, applicable in event driven mode
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* @tx_wm: Sender watermark, applicable in event driven mode
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* @rx_req: Receiver sets this bit if queue is empty
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* @tx_req: Sender sets this bit if queue is full
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* @rx_irq_status: Receiver sets this bit and triggers an interrupt to
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* the sender after packets are dequeued. Sender clears this bit
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* @tx_irq_status: Sender sets this bit and triggers an interrupt to
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* the receiver after packets are queued. Receiver clears this bit
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* @read_idx: Index till where receiver has consumed the packets from the queue.
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* @write_idx: Index till where sender has written the packets into the queue.
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*/
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struct iris_hfi_queue_header {
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u32 status;
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u32 start_addr;
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u16 queue_type;
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u16 header_type;
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u32 q_size;
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u32 pkt_size;
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u32 pkt_drop_cnt;
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u32 rx_wm;
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u32 tx_wm;
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u32 rx_req;
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u32 tx_req;
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u32 rx_irq_status;
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u32 tx_irq_status;
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u32 read_idx;
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u32 write_idx;
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};
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/**
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* struct iris_hfi_queue_table_header
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*
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* @version: Queue table version number
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* @size: Queue table size from version to last parametr in qhdr entry
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* @qhdr0_offset: Offset to the start of first qhdr
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* @qhdr_size: Queue header size in bytes
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* @num_q: Total number of queues in Queue table
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* @num_active_q: Total number of active queues
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* @device_addr: Device address of the queue
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* @name: Queue name in characters
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* @q_hdr: Array of queue headers
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*/
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struct iris_hfi_queue_table_header {
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u32 version;
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u32 size;
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u32 qhdr0_offset;
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u32 qhdr_size;
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u32 num_q;
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u32 num_active_q;
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void *device_addr;
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char name[256]; /* NUL-terminated array of characters */
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struct iris_hfi_queue_header q_hdr[IFACEQ_NUMQ];
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};
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struct iris_iface_q_info {
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struct iris_hfi_queue_header *qhdr;
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dma_addr_t device_addr;
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void *kernel_vaddr;
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};
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int iris_hfi_queues_init(struct iris_core *core);
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void iris_hfi_queues_deinit(struct iris_core *core);
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#endif
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