Marc Zyngier c870815609 KVM: arm/arm64: vgic-v3: Do not use Active+Pending state for a HW interrupt ...

commit 3d6e77ad14 upstream.

When an interrupt is injected with the HW bit set (indicating that
deactivation should be propagated to the physical distributor),
special care must be taken so that we never mark the corresponding
LR with the Active+Pending state (as the pending state is kept in
the physycal distributor).

Fixes: 59529f69f5 ("KVM: arm/arm64: vgic-new: Add GICv3 world switch backend")
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

2017-05-25 15:46:23 +02:00

..

hyp

KVM: arm/arm64: Move cntvoff to each timer context

2017-02-08 15:13:33 +00:00

vgic

KVM: arm/arm64: vgic-v3: Do not use Active+Pending state for a HW interrupt

2017-05-25 15:46:23 +02:00

aarch32.c

arm64: KVM: Make kvm_skip_instr32 available to HYP

2016-09-08 12:53:00 +02:00

arch_timer.c

KVM: arm/arm64: Emulate the EL1 phys timer registers

2017-02-08 15:13:37 +00:00

pmu.c

KVM: arm64: Fix the issues when guest PMCCFILTR is configured

2016-11-18 09:06:58 +00:00

trace.h

arm/arm64: KVM: Add tracepoints for vgic and timer

2015-10-22 23:01:48 +02:00