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995dedb7a4
[why] There are some registers for plane color that are skipped programming on resume. Need to add those as part of the sequence. [how] Add new function hook for programming plane color control. Reviewed-by: Duncan Ma <duncan.ma@amd.com> Acked-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Sung Joon Kim <sungkim@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
242 lines
7.6 KiB
C
242 lines
7.6 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright 2023 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dcn35_hubp.h"
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#include "reg_helper.h"
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#define REG(reg)\
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hubp2->hubp_regs->reg
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#define CTX \
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hubp2->base.ctx
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#undef FN
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#define FN(reg_name, field_name) \
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((const struct dcn35_hubp2_shift *)hubp2->hubp_shift)->field_name, \
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((const struct dcn35_hubp2_mask *)hubp2->hubp_mask)->field_name
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void hubp35_set_fgcg(struct hubp *hubp, bool enable)
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{
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struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
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REG_UPDATE(HUBP_CLK_CNTL, HUBP_FGCG_REP_DIS, !enable);
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}
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static void hubp35_init(struct hubp *hubp)
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{
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hubp3_init(hubp);
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hubp35_set_fgcg(hubp, hubp->ctx->dc->debug.enable_fine_grain_clock_gating.bits.dchub);
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/*do nothing for now for dcn3.5 or later*/
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}
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void hubp35_program_pixel_format(
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struct hubp *hubp,
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enum surface_pixel_format format)
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{
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struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
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uint32_t green_bar = 1;
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uint32_t red_bar = 3;
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uint32_t blue_bar = 2;
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/* swap for ABGR format */
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if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888
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|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
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|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS
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|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616
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|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
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red_bar = 2;
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blue_bar = 3;
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}
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REG_UPDATE_3(HUBPRET_CONTROL,
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CROSSBAR_SRC_Y_G, green_bar,
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CROSSBAR_SRC_CB_B, blue_bar,
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CROSSBAR_SRC_CR_R, red_bar);
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/* Mapping is same as ipp programming (cnvc) */
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switch (format) {
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case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 1);
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 3);
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
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case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 8);
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
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case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
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case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 10);
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
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case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /* we use crossbar already */
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
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case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 24);
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break;
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case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 65);
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break;
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case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 64);
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break;
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case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 67);
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break;
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case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 66);
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break;
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case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 12);
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 112);
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 113);
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break;
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case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 114);
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 118);
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 119);
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
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REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 116,
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ALPHA_PLANE_EN, 0);
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
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REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 116,
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ALPHA_PLANE_EN, 1);
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break;
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default:
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BREAK_TO_DEBUGGER();
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break;
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}
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/* don't see the need of program the xbar in DCN 1.0 */
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}
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void hubp35_program_surface_config(
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struct hubp *hubp,
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enum surface_pixel_format format,
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union dc_tiling_info *tiling_info,
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struct plane_size *plane_size,
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enum dc_rotation_angle rotation,
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struct dc_plane_dcc_param *dcc,
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bool horizontal_mirror,
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unsigned int compat_level)
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{
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struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
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hubp3_dcc_control_sienna_cichlid(hubp, dcc);
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hubp3_program_tiling(hubp2, tiling_info, format);
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hubp2_program_size(hubp, format, plane_size, dcc);
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hubp2_program_rotation(hubp, rotation, horizontal_mirror);
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hubp35_program_pixel_format(hubp, format);
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}
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struct hubp_funcs dcn35_hubp_funcs = {
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.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
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.hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
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.hubp_program_surface_flip_and_addr = hubp3_program_surface_flip_and_addr,
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.hubp_program_surface_config = hubp35_program_surface_config,
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.hubp_is_flip_pending = hubp2_is_flip_pending,
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.hubp_setup = hubp3_setup,
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.hubp_setup_interdependent = hubp2_setup_interdependent,
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.hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings,
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.set_blank = hubp2_set_blank,
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.dcc_control = hubp3_dcc_control,
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.mem_program_viewport = min_set_viewport,
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.set_cursor_attributes = hubp2_cursor_set_attributes,
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.set_cursor_position = hubp2_cursor_set_position,
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.hubp_clk_cntl = hubp2_clk_cntl,
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.hubp_vtg_sel = hubp2_vtg_sel,
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.dmdata_set_attributes = hubp3_dmdata_set_attributes,
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.dmdata_load = hubp2_dmdata_load,
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.dmdata_status_done = hubp2_dmdata_status_done,
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.hubp_read_state = hubp3_read_state,
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.hubp_clear_underflow = hubp2_clear_underflow,
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.hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
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.hubp_init = hubp35_init,
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.set_unbounded_requesting = hubp31_set_unbounded_requesting,
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.hubp_soft_reset = hubp31_soft_reset,
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.hubp_set_flip_int = hubp1_set_flip_int,
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.hubp_in_blank = hubp1_in_blank,
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.program_extended_blank = hubp31_program_extended_blank_value,
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};
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bool hubp35_construct(
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struct dcn20_hubp *hubp2,
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struct dc_context *ctx,
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uint32_t inst,
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const struct dcn_hubp2_registers *hubp_regs,
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const struct dcn35_hubp2_shift *hubp_shift,
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const struct dcn35_hubp2_mask *hubp_mask)
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{
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hubp2->base.funcs = &dcn35_hubp_funcs;
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hubp2->base.ctx = ctx;
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hubp2->hubp_regs = hubp_regs;
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hubp2->hubp_shift = (const struct dcn_hubp2_shift *)hubp_shift;
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hubp2->hubp_mask = (const struct dcn_hubp2_mask *)hubp_mask;
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hubp2->base.inst = inst;
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hubp2->base.opp_id = OPP_ID_INVALID;
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hubp2->base.mpcc_id = 0xf;
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return true;
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}
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