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62742d1266
The flags stored in the BO grew over time without following much a naming pattern. First of all, get rid of the _BIT suffix that was banned from everywhere else due to the guideline in drivers/gpu/drm/i915/i915_reg.h that xe kind of follows: Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name. Here the flags aren't for a register, but it's good practice to keep it consistent. Second divergence on names is the use or not of "CREATE". This is because most of the flags are passed to xe_bo_create*() family of functions, changing its behavior. However, since the flags are also stored in the bo itself and checked elsewhere in the code, it seems better to just omit the CREATE part. With those 2 guidelines, all the flags are given the form XE_BO_FLAG_<FLAG_NAME> with the following commands: git grep -le "XE_BO_" -- drivers/gpu/drm/xe | xargs sed -i \ -e "s/XE_BO_\([_A-Z0-9]*\)_BIT/XE_BO_\1/g" \ -e 's/XE_BO_CREATE_/XE_BO_FLAG_/g' git grep -le "XE_BO_" -- drivers/gpu/drm/xe | xargs sed -i -r \ -e 's/XE_BO_(DEFER_BACKING|SCANOUT|FIXED_PLACEMENT|PAGETABLE|NEEDS_CPU_ACCESS|NEEDS_UC|INTERNAL_TEST|INTERNAL_64K|GGTT_INVALIDATE)/XE_BO_FLAG_\1/g' And then the defines in drivers/gpu/drm/xe/xe_bo.h are adjusted to follow the coding style. Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240322142702.186529-3-lucas.demarchi@intel.com Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
106 lines
2.1 KiB
C
106 lines
2.1 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#include "xe_guc_hwconfig.h"
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#include <drm/drm_managed.h>
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#include "abi/guc_actions_abi.h"
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#include "xe_bo.h"
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#include "xe_device.h"
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#include "xe_gt.h"
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#include "xe_guc.h"
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#include "xe_map.h"
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static int send_get_hwconfig(struct xe_guc *guc, u64 ggtt_addr, u32 size)
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{
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u32 action[] = {
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XE_GUC_ACTION_GET_HWCONFIG,
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lower_32_bits(ggtt_addr),
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upper_32_bits(ggtt_addr),
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size,
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};
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return xe_guc_mmio_send(guc, action, ARRAY_SIZE(action));
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}
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static int guc_hwconfig_size(struct xe_guc *guc, u32 *size)
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{
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int ret = send_get_hwconfig(guc, 0, 0);
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if (ret < 0)
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return ret;
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*size = ret;
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return 0;
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}
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static int guc_hwconfig_copy(struct xe_guc *guc)
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{
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int ret = send_get_hwconfig(guc, xe_bo_ggtt_addr(guc->hwconfig.bo),
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guc->hwconfig.size);
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if (ret < 0)
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return ret;
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return 0;
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}
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int xe_guc_hwconfig_init(struct xe_guc *guc)
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{
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struct xe_device *xe = guc_to_xe(guc);
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struct xe_gt *gt = guc_to_gt(guc);
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struct xe_tile *tile = gt_to_tile(gt);
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struct xe_bo *bo;
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u32 size;
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int err;
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/* Initialization already done */
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if (guc->hwconfig.bo)
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return 0;
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/*
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* All hwconfig the same across GTs so only GT0 needs to be configured
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*/
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if (gt->info.id != XE_GT0)
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return 0;
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/* ADL_P, DG2+ supports hwconfig table */
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if (GRAPHICS_VERx100(xe) < 1255 && xe->info.platform != XE_ALDERLAKE_P)
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return 0;
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err = guc_hwconfig_size(guc, &size);
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if (err)
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return err;
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if (!size)
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return -EINVAL;
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bo = xe_managed_bo_create_pin_map(xe, tile, PAGE_ALIGN(size),
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XE_BO_FLAG_SYSTEM |
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XE_BO_FLAG_GGTT |
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XE_BO_FLAG_GGTT_INVALIDATE);
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if (IS_ERR(bo))
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return PTR_ERR(bo);
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guc->hwconfig.bo = bo;
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guc->hwconfig.size = size;
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return guc_hwconfig_copy(guc);
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}
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u32 xe_guc_hwconfig_size(struct xe_guc *guc)
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{
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return !guc->hwconfig.bo ? 0 : guc->hwconfig.size;
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}
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void xe_guc_hwconfig_copy(struct xe_guc *guc, void *dst)
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{
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struct xe_device *xe = guc_to_xe(guc);
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XE_WARN_ON(!guc->hwconfig.bo);
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xe_map_memcpy_from(xe, dst, &guc->hwconfig.bo->vmap, 0,
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guc->hwconfig.size);
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}
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