Files
linux/drivers/gpu/drm/amd/display/dc
loanchen f88192d233 drm/amd/display: Correct register address in dcn35
[Why]
the offset address of mmCLK5_spll_field_8 was incorrect for dcn35
which causes SSC not to be enabled.

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Lo-An Chen <lo-an.chen@amd.com>
Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2025-01-28 16:23:30 -05:00
..
2024-07-23 17:07:11 -04:00
2024-07-27 17:31:26 -04:00
2024-07-23 17:35:45 -04:00
2024-07-23 17:07:10 -04:00
2025-01-06 14:44:28 -05:00
2025-01-10 12:12:47 -05:00
2024-07-27 17:31:26 -04:00