Maxime Ripard c16f3c1d77 drm/vc4: Increase the core clock based on HVS load ...

Depending on a given HVS output (HVS to PixelValves) and input (planes
attached to a channel) load, the HVS needs for the core clock to be
raised above its boot time default.

Failing to do so will result in a vblank timeout and a stalled display
pipeline.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>

2022-03-21 16:03:45 +00:00

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