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3b500ff37c
The sdmmc controller's CIU(Card Interface Unit) clock's phase can be adjusted through the register in the system manager. Add the binding "altr,sysmgr-syscon" to the SDMMC node for the driver to access the system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to designate the smpsel and drvsel properties for the CIU clock. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
38 lines
579 B
Plaintext
38 lines
579 B
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*/
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/dts-v1/;
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/* First 4KB has trampoline code for secondary cores. */
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/memreserve/ 0x00000000 0x0001000;
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#include "socfpga.dtsi"
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/ {
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soc {
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clkmgr@ffd04000 {
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clocks {
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osc1 {
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clock-frequency = <25000000>;
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};
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};
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};
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mmc0: mmc@ff704000 {
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broken-cd;
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bus-width = <4>;
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cap-mmc-highspeed;
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cap-sd-highspeed;
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clk-phase-sd-hs = <0>, <135>;
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};
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sysmgr@ffd08000 {
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cpu1-start-addr = <0xffd080c4>;
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};
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};
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};
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&watchdog0 {
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status = "okay";
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};
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