mirror of
https://github.com/raspberrypi/linux.git
synced 2025-12-24 11:02:51 +00:00
01f3cbb296
Pull ARM SoC DT updates from Arnd Bergmann:
"The devicetree changes contain exactly 1000 non-merge changesets,
including a number of new arm64 SoC variants from Qualcomm and Apple,
as well as the Renesas r9a07g043f/u chip in both arm64 and riscv
variants.
While we have occasionally merged support for non-arm SoCs in the
past, this is now the normal path for riscv devicetree files.
The most notable changes, by SoC platform, are:
- The Apple T6000 (M1 Pro), T6001 (M1 Max) and T6002 (M1 Ultra) chips
now have initial support. This is particularly nice as I am typing
this on a T6002 Mac Studio with only a small number of driver
patches.
- Qualcomm MSM8996 Pro (Snapdragon 821), SM6115 (Snapdragon 662),
SM4250 (Snapdragon 460), SM6375 (Snapdragon 695), SDM670
(Snapdragon 670), MSM8976 (Snapdragon 652) and MSM8956 (Snapdragon
650) are all mobile phone chips that are closely related to others
we already support.
Adding those helps support more phones and we add several models
from Sony (Xperia 10 IV, 5 IV, X, and X compact), OnePlus (One, 3,
3T, and Nord N100), Xiaomi (Poco F1, Mi6), Huawei (Watch) and
Google (Pixel 3a).
There are also new variants of the Herobrine and Trogdor chromebook
motherboards. SA8540P is an automotive SoC used in the Qdrive-3
development platform
- Rockchips gains no new SoC variants, but a lot of new boards: three
mobile gaming systems based on RK3326 Odroid-Go/rg351 family, two
more Anbernic gaming systems based on RK3566 and a number of other
RK356x based single-board computers.
- Renesas RZ/G2UL (r9a07g043) was already supported for arm64, but as
the newly added RZ/Five is based on the same design, this now gets
reorganized in order to share most of the dts description between
the two and add the RZ/Five SMARC EVK board support.
Aside from that, there are the usual changes all over the tree:
- New boards on other platforms contain two ASpeed BMC users, two
Broadcom based Wifi routers, Zyxel NSA310S NAS, the i.MX6 based
Kobo Aura2 ebook reader, two i.MX8 based development boards, two
Uniphier Pro5 development boards, the STM32MP1 testbench board from
DHCOR, the TI K3 based BeagleBone AI-64 board, and the Mediatek
Helio X10 based Sony Xperia M5 phone.
- The Starfive JH7100 source gets reorganized in order to support the
VisionFive V1 board.
- Minor updates and cleanups for Intel SoCFPGA, Marvell PXA168, TI,
ST, NXP, Apple, Broadcom, Juno, Marvell MVEBU, at91, nuvoton,
Tegra, Mediatek, Renesas, Hisilicon, Allwinner, Samsung, ux500,
spear, ... The treewide cleanups now have a lot of fixes for cache
nodes and other binding violoations.
- Somewhat larger sets of reworks for NVIDIA Tegra, Qualcomm and
Renesas platforms, adding a lot more on-chip device support
- A rework of the way that DTB overlays are built"
* tag 'soc-dt-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (979 commits)
arm64: dts: apple: t6002: Fix GPU power domains
arm64: dts: apple: t600x-pmgr: Fix search & replace typo
arm64: dts: apple: Add t8103 L1/L2 cache properties and nodes
arm64: dts: apple: Rename dart-sio* to sio-dart*
arch: arm64: apple: t600x: Use standard "iommu" node name
arch: arm64: apple: t8103: Use standard "iommu" node name
ARM: dts: socfpga: Fix pca9548 i2c-mux node name
dt-bindings: iio: adc: qcom,spmi-vadc: fix PM8350 define
dt-bindings: iio: adc: qcom,spmi-vadc: extend example
arm64: dts: qcom: sc8280xp: fix UFS DMA coherency
arm64: dts: qcom: sc7280: Add DT for sc7280-herobrine-zombie
arm64: dts: qcom: sm8250-sony-xperia-edo: fix no-mmc property for SDHCI
arm64: dts: qcom: sdm845-sony-xperia-tama: fix no-mmc property for SDHCI
arm64: dts: qcom: sda660-inforce-ifc6560: fix no-mmc property for SDHCI
arm64: dts: qcom: sa8155p-adp: fix no-mmc property for SDHCI
arm64: dts: qcom: qrb5165-rb: fix no-mmc property for SDHCI
arm64: dts: qcom: sm8450: align MMC node names with dtschema
arm64: dts: qcom: sc7180-trogdor: use generic node names
arm64: dts: qcom: sm8450-hdk: add sound support
arm64: dts: qcom: sm8450: add Soundwire and LPASS
...
641 lines
17 KiB
Plaintext
641 lines
17 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2022 NXP
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*/
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#include <dt-bindings/clock/imx93-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/fsl,imx93-power.h>
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#include "imx93-pinfunc.h"
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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i2c0 = &lpi2c1;
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i2c1 = &lpi2c2;
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i2c2 = &lpi2c3;
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i2c3 = &lpi2c4;
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i2c4 = &lpi2c5;
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i2c5 = &lpi2c6;
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i2c6 = &lpi2c7;
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i2c7 = &lpi2c8;
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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mmc2 = &usdhc3;
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serial0 = &lpuart1;
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serial1 = &lpuart2;
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serial2 = &lpuart3;
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serial3 = &lpuart4;
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serial4 = &lpuart5;
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serial5 = &lpuart6;
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serial6 = &lpuart7;
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serial7 = &lpuart8;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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A55_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0>;
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enable-method = "psci";
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#cooling-cells = <2>;
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};
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A55_1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x100>;
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enable-method = "psci";
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#cooling-cells = <2>;
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};
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};
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osc_32k: clock-osc-32k {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "osc_32k";
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};
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osc_24m: clock-osc-24m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "osc_24m";
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};
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clk_ext1: clock-ext1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <133000000>;
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clock-output-names = "clk_ext1";
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};
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pmu {
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compatible = "arm,cortex-a55-pmu";
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interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <24000000>;
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arm,no-tick-in-suspend;
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interrupt-parent = <&gic>;
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};
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gic: interrupt-controller@48000000 {
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compatible = "arm,gic-v3";
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reg = <0 0x48000000 0 0x10000>,
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<0 0x48040000 0 0xc0000>;
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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};
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soc@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x0 0x80000000>,
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<0x28000000 0x0 0x28000000 0x10000000>;
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aips1: bus@44000000 {
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compatible = "fsl,aips-bus", "simple-bus";
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reg = <0x44000000 0x800000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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anomix_ns_gpr: syscon@44210000 {
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compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon";
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reg = <0x44210000 0x1000>;
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};
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mu1: mailbox@44230000 {
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compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
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reg = <0x44230000 0x10000>;
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_MU1_B_GATE>;
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#mbox-cells = <2>;
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status = "disabled";
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};
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system_counter: timer@44290000 {
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compatible = "nxp,sysctr-timer";
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reg = <0x44290000 0x30000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&osc_24m>;
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clock-names = "per";
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nxp,no-divider;
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};
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tpm2: pwm@44320000 {
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compatible = "fsl,imx7ulp-pwm";
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reg = <0x44320000 0x10000>;
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clocks = <&clk IMX93_CLK_TPM2_GATE>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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lpi2c1: i2c@44340000 {
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compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x44340000 0x10000>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPI2C1_GATE>,
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<&clk IMX93_CLK_BUS_AON>;
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clock-names = "per", "ipg";
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status = "disabled";
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};
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lpi2c2: i2c@44350000 {
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compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x44350000 0x10000>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPI2C2_GATE>,
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<&clk IMX93_CLK_BUS_AON>;
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clock-names = "per", "ipg";
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status = "disabled";
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};
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lpspi1: spi@44360000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
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reg = <0x44360000 0x10000>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPSPI1_GATE>,
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<&clk IMX93_CLK_BUS_AON>;
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clock-names = "per", "ipg";
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status = "disabled";
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};
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lpspi2: spi@44370000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
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reg = <0x44370000 0x10000>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPSPI2_GATE>,
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<&clk IMX93_CLK_BUS_AON>;
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clock-names = "per", "ipg";
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status = "disabled";
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};
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lpuart1: serial@44380000 {
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compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
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reg = <0x44380000 0x1000>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPUART1_GATE>;
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clock-names = "ipg";
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status = "disabled";
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};
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lpuart2: serial@44390000 {
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compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
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reg = <0x44390000 0x1000>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPUART2_GATE>;
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clock-names = "ipg";
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status = "disabled";
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};
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iomuxc: pinctrl@443c0000 {
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compatible = "fsl,imx93-iomuxc";
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reg = <0x443c0000 0x10000>;
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status = "okay";
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};
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clk: clock-controller@44450000 {
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compatible = "fsl,imx93-ccm";
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reg = <0x44450000 0x10000>;
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#clock-cells = <1>;
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clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>;
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clock-names = "osc_32k", "osc_24m", "clk_ext1";
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status = "okay";
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};
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src: system-controller@44460000 {
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compatible = "fsl,imx93-src", "syscon";
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reg = <0x44460000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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mediamix: power-domain@44462400 {
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compatible = "fsl,imx93-src-slice";
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reg = <0x44462400 0x400>, <0x44465800 0x400>;
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#power-domain-cells = <0>;
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clocks = <&clk IMX93_CLK_MEDIA_AXI>,
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<&clk IMX93_CLK_MEDIA_APB>;
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};
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mlmix: power-domain@44461800 {
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compatible = "fsl,imx93-src-slice";
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reg = <0x44461800 0x400>, <0x44464800 0x400>;
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#power-domain-cells = <0>;
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clocks = <&clk IMX93_CLK_ML_APB>,
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<&clk IMX93_CLK_ML>;
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};
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};
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anatop: anatop@44480000 {
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compatible = "fsl,imx93-anatop", "syscon";
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reg = <0x44480000 0x10000>;
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};
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};
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aips2: bus@42000000 {
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compatible = "fsl,aips-bus", "simple-bus";
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reg = <0x42000000 0x800000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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wakeupmix_gpr: syscon@42420000 {
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compatible = "fsl,imx93-wakeupmix-syscfg", "syscon";
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reg = <0x42420000 0x1000>;
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};
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mu2: mailbox@42440000 {
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compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
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reg = <0x42440000 0x10000>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_MU2_B_GATE>;
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#mbox-cells = <2>;
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status = "disabled";
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};
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tpm4: pwm@424f0000 {
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compatible = "fsl,imx7ulp-pwm";
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reg = <0x424f0000 0x10000>;
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clocks = <&clk IMX93_CLK_TPM4_GATE>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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tpm5: pwm@42500000 {
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compatible = "fsl,imx7ulp-pwm";
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reg = <0x42500000 0x10000>;
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clocks = <&clk IMX93_CLK_TPM5_GATE>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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tpm6: pwm@42510000 {
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compatible = "fsl,imx7ulp-pwm";
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reg = <0x42510000 0x10000>;
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clocks = <&clk IMX93_CLK_TPM6_GATE>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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lpi2c3: i2c@42530000 {
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compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x42530000 0x10000>;
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPI2C3_GATE>,
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<&clk IMX93_CLK_BUS_WAKEUP>;
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clock-names = "per", "ipg";
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status = "disabled";
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};
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lpi2c4: i2c@42540000 {
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compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x42540000 0x10000>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPI2C4_GATE>,
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<&clk IMX93_CLK_BUS_WAKEUP>;
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clock-names = "per", "ipg";
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status = "disabled";
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};
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lpspi3: spi@42550000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
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reg = <0x42550000 0x10000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPSPI3_GATE>,
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<&clk IMX93_CLK_BUS_WAKEUP>;
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clock-names = "per", "ipg";
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status = "disabled";
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};
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lpspi4: spi@42560000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
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reg = <0x42560000 0x10000>;
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPSPI4_GATE>,
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<&clk IMX93_CLK_BUS_WAKEUP>;
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clock-names = "per", "ipg";
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status = "disabled";
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};
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lpuart3: serial@42570000 {
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compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
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reg = <0x42570000 0x1000>;
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPUART3_GATE>;
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clock-names = "ipg";
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status = "disabled";
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};
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lpuart4: serial@42580000 {
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compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
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reg = <0x42580000 0x1000>;
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPUART4_GATE>;
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clock-names = "ipg";
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status = "disabled";
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};
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lpuart5: serial@42590000 {
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compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
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reg = <0x42590000 0x1000>;
|
|
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPUART5_GATE>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart6: serial@425a0000 {
|
|
compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
|
|
reg = <0x425a0000 0x1000>;
|
|
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPUART6_GATE>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart7: serial@42690000 {
|
|
compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
|
|
reg = <0x42690000 0x1000>;
|
|
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPUART7_GATE>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart8: serial@426a0000 {
|
|
compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
|
|
reg = <0x426a0000 0x1000>;
|
|
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPUART8_GATE>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpi2c5: i2c@426b0000 {
|
|
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
|
|
reg = <0x426b0000 0x10000>;
|
|
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPI2C5_GATE>,
|
|
<&clk IMX93_CLK_BUS_WAKEUP>;
|
|
clock-names = "per", "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpi2c6: i2c@426c0000 {
|
|
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
|
|
reg = <0x426c0000 0x10000>;
|
|
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPI2C6_GATE>,
|
|
<&clk IMX93_CLK_BUS_WAKEUP>;
|
|
clock-names = "per", "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpi2c7: i2c@426d0000 {
|
|
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
|
|
reg = <0x426d0000 0x10000>;
|
|
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPI2C7_GATE>,
|
|
<&clk IMX93_CLK_BUS_WAKEUP>;
|
|
clock-names = "per", "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpi2c8: i2c@426e0000 {
|
|
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
|
|
reg = <0x426e0000 0x10000>;
|
|
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPI2C8_GATE>,
|
|
<&clk IMX93_CLK_BUS_WAKEUP>;
|
|
clock-names = "per", "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpspi5: spi@426f0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
|
|
reg = <0x426f0000 0x10000>;
|
|
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPSPI5_GATE>,
|
|
<&clk IMX93_CLK_BUS_WAKEUP>;
|
|
clock-names = "per", "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpspi6: spi@42700000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
|
|
reg = <0x42700000 0x10000>;
|
|
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPSPI6_GATE>,
|
|
<&clk IMX93_CLK_BUS_WAKEUP>;
|
|
clock-names = "per", "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpspi7: spi@42710000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
|
|
reg = <0x42710000 0x10000>;
|
|
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPSPI7_GATE>,
|
|
<&clk IMX93_CLK_BUS_WAKEUP>;
|
|
clock-names = "per", "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpspi8: spi@42720000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
|
|
reg = <0x42720000 0x10000>;
|
|
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPSPI8_GATE>,
|
|
<&clk IMX93_CLK_BUS_WAKEUP>;
|
|
clock-names = "per", "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
};
|
|
|
|
aips3: bus@42800000 {
|
|
compatible = "fsl,aips-bus", "simple-bus";
|
|
reg = <0x42800000 0x800000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
usdhc1: mmc@42850000 {
|
|
compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
|
|
reg = <0x42850000 0x10000>;
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
|
|
<&clk IMX93_CLK_WAKEUP_AXI>,
|
|
<&clk IMX93_CLK_USDHC1_GATE>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <8>;
|
|
fsl,tuning-start-tap = <20>;
|
|
fsl,tuning-step= <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc2: mmc@42860000 {
|
|
compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
|
|
reg = <0x42860000 0x10000>;
|
|
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
|
|
<&clk IMX93_CLK_WAKEUP_AXI>,
|
|
<&clk IMX93_CLK_USDHC2_GATE>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
fsl,tuning-start-tap = <20>;
|
|
fsl,tuning-step= <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc3: mmc@428b0000 {
|
|
compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
|
|
reg = <0x428b0000 0x10000>;
|
|
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
|
|
<&clk IMX93_CLK_WAKEUP_AXI>,
|
|
<&clk IMX93_CLK_USDHC3_GATE>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
fsl,tuning-start-tap = <20>;
|
|
fsl,tuning-step= <2>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
gpio2: gpio@43810080 {
|
|
compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
|
|
reg = <0x43810080 0x1000>, <0x43810040 0x40>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&clk IMX93_CLK_GPIO2_GATE>,
|
|
<&clk IMX93_CLK_GPIO2_GATE>;
|
|
clock-names = "gpio", "port";
|
|
gpio-ranges = <&iomuxc 0 4 30>;
|
|
};
|
|
|
|
gpio3: gpio@43820080 {
|
|
compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
|
|
reg = <0x43820080 0x1000>, <0x43820040 0x40>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&clk IMX93_CLK_GPIO3_GATE>,
|
|
<&clk IMX93_CLK_GPIO3_GATE>;
|
|
clock-names = "gpio", "port";
|
|
gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>,
|
|
<&iomuxc 26 34 2>, <&iomuxc 28 0 4>;
|
|
};
|
|
|
|
gpio4: gpio@43830080 {
|
|
compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
|
|
reg = <0x43830080 0x1000>, <0x43830040 0x40>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&clk IMX93_CLK_GPIO4_GATE>,
|
|
<&clk IMX93_CLK_GPIO4_GATE>;
|
|
clock-names = "gpio", "port";
|
|
gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>;
|
|
};
|
|
|
|
gpio1: gpio@47400080 {
|
|
compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
|
|
reg = <0x47400080 0x1000>, <0x47400040 0x40>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&clk IMX93_CLK_GPIO1_GATE>,
|
|
<&clk IMX93_CLK_GPIO1_GATE>;
|
|
clock-names = "gpio", "port";
|
|
gpio-ranges = <&iomuxc 0 92 16>;
|
|
};
|
|
|
|
s4muap: mailbox@47520000 {
|
|
compatible = "fsl,imx93-mu-s4";
|
|
reg = <0x47520000 0x10000>;
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "tx", "rx";
|
|
#mbox-cells = <2>;
|
|
};
|
|
|
|
media_blk_ctrl: system-controller@4ac10000 {
|
|
compatible = "fsl,imx93-media-blk-ctrl", "syscon";
|
|
reg = <0x4ac10000 0x10000>;
|
|
power-domains = <&mediamix>;
|
|
clocks = <&clk IMX93_CLK_MEDIA_APB>,
|
|
<&clk IMX93_CLK_MEDIA_AXI>,
|
|
<&clk IMX93_CLK_NIC_MEDIA_GATE>,
|
|
<&clk IMX93_CLK_MEDIA_DISP_PIX>,
|
|
<&clk IMX93_CLK_CAM_PIX>,
|
|
<&clk IMX93_CLK_PXP_GATE>,
|
|
<&clk IMX93_CLK_LCDIF_GATE>,
|
|
<&clk IMX93_CLK_ISI_GATE>,
|
|
<&clk IMX93_CLK_MIPI_CSI_GATE>,
|
|
<&clk IMX93_CLK_MIPI_DSI_GATE>;
|
|
clock-names = "apb", "axi", "nic", "disp", "cam",
|
|
"pxp", "lcdif", "isi", "csi", "dsi";
|
|
#power-domain-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|