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2f0300a694
DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Merge subnodes named 'pinconf' and 'pinmux' into one entry, add function where missing (required by bindings for GPIOs) and reorganize overriding pins by boards. Split the SPI and UART configuration into separate nodes 1. SPI (MOSI, MISO, SCLK), SPI chip-select, SPI chip-select via GPIO, 2. UART per each pin: TX, RX and optional CTS/RTS. This allows each board to customize them easily without adding any new nodes. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221020225135.31750-4-krzysztof.kozlowski@linaro.org
196 lines
3.3 KiB
Plaintext
196 lines
3.3 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Google Trogdor board device tree source
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*
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* Copyright 2020 Google LLC.
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*/
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/dts-v1/;
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#include "sc7180-trogdor.dtsi"
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/* Must come after sc7180-trogdor.dtsi to modify cros_ec */
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#include <arm/cros-ec-keyboard.dtsi>
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#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
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/ {
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model = "Google Trogdor (rev1+)";
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compatible = "google,trogdor", "qcom,sc7180";
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};
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&ap_tp_i2c {
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status = "okay";
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};
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ap_ts_pen_1v8: &i2c4 {
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status = "okay";
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clock-frequency = <400000>;
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ap_ts: touchscreen@10 {
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compatible = "elan,ekth3500";
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reg = <0x10>;
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pinctrl-names = "default";
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pinctrl-0 = <&ts_int_l>, <&ts_reset_l>;
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interrupt-parent = <&tlmm>;
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interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
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vcc33-supply = <&pp3300_ts>;
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reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>;
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};
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};
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&panel {
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compatible = "auo,b116xa01";
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};
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&sdhc_2 {
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status = "okay";
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};
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&trackpad {
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interrupts = <58 IRQ_TYPE_EDGE_FALLING>;
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};
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&usb_hub_2_x {
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vdd-supply = <&pp3300_l7c>;
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};
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&usb_hub_3_x {
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vdd-supply = <&pp3300_l7c>;
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};
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/* PINCTRL - modifications to sc7180-trogdor.dtsi */
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&trackpad_int_1v8_odl {
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pins = "gpio58";
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};
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/* PINCTRL - board-specific pinctrl */
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&tlmm {
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gpio-line-names = "ESIM_MISO",
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"ESIM_MOSI",
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"ESIM_CLK",
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"ESIM_CS_L",
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"FP_TO_AP_IRQ_L",
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"FP_RST_L",
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"AP_TP_I2C_SDA",
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"AP_TP_I2C_SCL",
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"TS_RESET_L",
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"TS_INT_L",
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"FPMCU_BOOT0",
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"EDP_BRIJ_IRQ",
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"AP_EDP_BKLTEN",
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"",
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"",
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"EDP_BRIJ_I2C_SDA",
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"EDP_BRIJ_I2C_SCL",
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"HUB_RST_L",
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"PEN_RST_ODL",
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"AP_RAM_ID1",
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"AP_RAM_ID2",
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"PEN_IRQ_L",
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"FPMCU_SEL",
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"AMP_EN",
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"P_SENSOR_INT_L",
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"AP_SAR_SENSOR_SDA",
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"AP_SAR_SENSOR_SCL",
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"",
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"HP_IRQ",
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"AP_RAM_ID0",
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"EN_PP3300_DX_EDP",
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"AP_BRD_ID2",
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"BRIJ_SUSPEND",
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"AP_BRD_ID0",
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"AP_H1_SPI_MISO",
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"AP_H1_SPI_MOSI",
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"AP_H1_SPI_CLK",
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"AP_H1_SPI_CS_L",
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"",
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"",
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"",
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"",
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"H1_AP_INT_ODL",
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"",
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"UART_AP_TX_DBG_RX",
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"UART_DBG_TX_AP_RX",
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"HP_I2C_SDA",
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"HP_I2C_SCL",
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"FORCED_USB_BOOT",
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"",
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"",
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"AMP_DIN",
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"PEN_PDCT_L",
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"HP_BCLK",
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"HP_LRCLK",
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"HP_DOUT",
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"HP_DIN",
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"HP_MCLK",
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"TRACKPAD_INT_1V8_ODL",
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"AP_EC_SPI_MISO",
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"AP_EC_SPI_MOSI",
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"AP_EC_SPI_CLK",
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"AP_EC_SPI_CS_L",
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"AP_SPI_CLK",
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"AP_SPI_MOSI",
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"AP_SPI_MISO",
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/*
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* AP_FLASH_WP_L is crossystem ABI. Schematics
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* call it BIOS_FLASH_WP_L.
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*/
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"AP_FLASH_WP_L",
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"DBG_SPI_HOLD_L",
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"AP_SPI_CS0_L",
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"SD_CD_ODL",
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"",
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"",
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"",
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"",
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"",
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"UIM2_DATA",
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"UIM2_CLK",
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"UIM2_RST",
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"UIM2_PRESENT",
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"UIM1_DATA",
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"UIM1_CLK",
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"UIM1_RST",
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"",
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"EN_PP3300_CODEC",
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"EN_PP3300_HUB",
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"",
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"AP_SPI_FP_MISO",
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"AP_SPI_FP_MOSI",
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"AP_SPI_FP_CLK",
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"AP_SPI_FP_CS_L",
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"AP_SKU_ID1",
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"AP_RST_REQ",
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"",
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"AP_BRD_ID1",
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"AP_EC_INT_L",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"EDP_BRIJ_EN",
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"AP_SKU_ID0",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"AP_TS_PEN_I2C_SDA",
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"AP_TS_PEN_I2C_SCL",
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"DP_HOT_PLUG_DET",
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"EC_IN_RW_ODL";
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};
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