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d49166646e
Add device trees for both configs used by the Aries Embedded M100PFSEVP. The M100OFSEVP consists of a MPFS250T on a SOM, featuring: - 2GB DDR4 SDRAM dedicated to the HMS - 512MB DDR4 SDRAM dedicated to the FPGA - 32 MB SPI NOR Flash - 4 GByte eMMC and a carrier board with: - 2x Gigabit Ethernet - USB - 2x UART - 2x CAN - TFT connector - HSMC extension connector - 3x PMOD extension connectors - microSD-card slot Link: https://www.aries-embedded.com/polarfire-soc-fpga-microsemi-m100pfs-som-mpfs025t-pcie-serdes Link: https://www.aries-embedded.com/evaluation-kit/fpga/polarfire-microchip-soc-fpga-m100pfsevp-riscv-hsmc-pmod Link: https://downloads.aries-embedded.de/products/M100PFS/Hardware/M100PFSEVP-Schematics.pdf Co-developed-by: Wolfgang Grandegger <wg@aries-embedded.de> Signed-off-by: Wolfgang Grandegger <wg@aries-embedded.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
7 lines
331 B
Makefile
7 lines
331 B
Makefile
# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
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dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb
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dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
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dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb
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obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
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