Michael Strauss 54e9ea3d5d drm/amd/display: Fix DCN2.1 default DSC clocks ...

[WHY]
Low dscclk in high vlevels blocks some DSC modes.

[HOW]
Update dscclk to 1/3 of dispclk.

Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2022-12-06 10:16:02 -05:00

..

dcn20_fpu.c

drm/amd/display: Fix DCN2.1 default DSC clocks

2022-12-06 10:16:02 -05:00

dcn20_fpu.h

drm/amd/display: Remove FPU operations from dcn201 resources

2022-07-25 17:16:08 -04:00

display_mode_vba_20.c

drm/amd/display: DETBufferSizeInKbyte variable type modifications

2021-05-10 18:10:34 -04:00

display_mode_vba_20.h

…

display_mode_vba_20v2.c

drm/amd/display: Optimizations for DML math

2022-09-13 14:32:59 -04:00

display_mode_vba_20v2.h

…

display_rq_dlg_calc_20.c

drm/amdgpu/display: Remove t_srx_delay_us.

2022-01-25 17:54:23 -05:00

display_rq_dlg_calc_20.h

drm/amd/display: Pass display_pipe_params_st as const in DML

2021-09-23 15:17:29 -04:00

display_rq_dlg_calc_20v2.c

drm/amdgpu/display: Remove t_srx_delay_us.

2022-01-25 17:54:23 -05:00

display_rq_dlg_calc_20v2.h

drm/amd/display: Pass display_pipe_params_st as const in DML

2021-09-23 15:17:29 -04:00