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Errata: The ptp_clock_hi rollsover to zero one clock cycle before it reaches one second boundary. As a result, the pps threshold comparison fails after one second and the pps output signal won't toggle further. This patch workarounds the issue by programming the pps_lo_incr register to 500msec minus one clock cycle period, ensuring that the pps threshold comparison succeeds at one second rollover boundary and pps edge toggles. After that point, the driver will have enough time (~500msec) to reset the pps threshold value. After each one second boundary, hrtimer is invoked which resets the pps threshold value. Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Signed-off-by: Rakesh Babu Saladi <rsaladi2@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
399 lines
8.6 KiB
C
399 lines
8.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Marvell RVU Ethernet driver
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*
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* Copyright (C) 2020 Marvell.
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*
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*/
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#include <linux/module.h>
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#include "otx2_common.h"
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#include "otx2_ptp.h"
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static u64 otx2_ptp_get_clock(struct otx2_ptp *ptp)
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{
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struct ptp_req *req;
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struct ptp_rsp *rsp;
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int err;
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if (!ptp->nic)
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return 0;
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req = otx2_mbox_alloc_msg_ptp_op(&ptp->nic->mbox);
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if (!req)
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return 0;
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req->op = PTP_OP_GET_CLOCK;
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err = otx2_sync_mbox_msg(&ptp->nic->mbox);
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if (err)
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return 0;
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rsp = (struct ptp_rsp *)otx2_mbox_get_rsp(&ptp->nic->mbox.mbox, 0,
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&req->hdr);
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if (IS_ERR(rsp))
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return 0;
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return rsp->clk;
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}
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static int otx2_ptp_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm)
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{
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struct otx2_ptp *ptp = container_of(ptp_info, struct otx2_ptp,
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ptp_info);
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struct ptp_req *req;
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if (!ptp->nic)
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return -ENODEV;
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req = otx2_mbox_alloc_msg_ptp_op(&ptp->nic->mbox);
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if (!req)
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return -ENOMEM;
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req->op = PTP_OP_ADJFINE;
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req->scaled_ppm = scaled_ppm;
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return otx2_sync_mbox_msg(&ptp->nic->mbox);
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}
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static int ptp_set_thresh(struct otx2_ptp *ptp, u64 thresh)
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{
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struct ptp_req *req;
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if (!ptp->nic)
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return -ENODEV;
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req = otx2_mbox_alloc_msg_ptp_op(&ptp->nic->mbox);
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if (!req)
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return -ENOMEM;
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req->op = PTP_OP_SET_THRESH;
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req->thresh = thresh;
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return otx2_sync_mbox_msg(&ptp->nic->mbox);
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}
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static int ptp_extts_on(struct otx2_ptp *ptp, int on)
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{
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struct ptp_req *req;
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if (!ptp->nic)
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return -ENODEV;
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req = otx2_mbox_alloc_msg_ptp_op(&ptp->nic->mbox);
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if (!req)
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return -ENOMEM;
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req->op = PTP_OP_EXTTS_ON;
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req->extts_on = on;
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return otx2_sync_mbox_msg(&ptp->nic->mbox);
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}
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static u64 ptp_cc_read(const struct cyclecounter *cc)
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{
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struct otx2_ptp *ptp = container_of(cc, struct otx2_ptp, cycle_counter);
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return otx2_ptp_get_clock(ptp);
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}
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static u64 ptp_tstmp_read(struct otx2_ptp *ptp)
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{
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struct ptp_req *req;
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struct ptp_rsp *rsp;
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int err;
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if (!ptp->nic)
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return 0;
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req = otx2_mbox_alloc_msg_ptp_op(&ptp->nic->mbox);
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if (!req)
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return 0;
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req->op = PTP_OP_GET_TSTMP;
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err = otx2_sync_mbox_msg(&ptp->nic->mbox);
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if (err)
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return 0;
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rsp = (struct ptp_rsp *)otx2_mbox_get_rsp(&ptp->nic->mbox.mbox, 0,
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&req->hdr);
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if (IS_ERR(rsp))
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return 0;
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return rsp->clk;
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}
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static void otx2_get_ptpclock(struct otx2_ptp *ptp, u64 *tstamp)
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{
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struct otx2_nic *pfvf = ptp->nic;
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mutex_lock(&pfvf->mbox.lock);
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*tstamp = timecounter_read(&ptp->time_counter);
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mutex_unlock(&pfvf->mbox.lock);
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}
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static int otx2_ptp_adjtime(struct ptp_clock_info *ptp_info, s64 delta)
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{
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struct otx2_ptp *ptp = container_of(ptp_info, struct otx2_ptp,
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ptp_info);
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struct otx2_nic *pfvf = ptp->nic;
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mutex_lock(&pfvf->mbox.lock);
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timecounter_adjtime(&ptp->time_counter, delta);
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mutex_unlock(&pfvf->mbox.lock);
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return 0;
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}
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static int otx2_ptp_gettime(struct ptp_clock_info *ptp_info,
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struct timespec64 *ts)
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{
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struct otx2_ptp *ptp = container_of(ptp_info, struct otx2_ptp,
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ptp_info);
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u64 tstamp;
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otx2_get_ptpclock(ptp, &tstamp);
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*ts = ns_to_timespec64(tstamp);
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return 0;
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}
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static int otx2_ptp_settime(struct ptp_clock_info *ptp_info,
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const struct timespec64 *ts)
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{
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struct otx2_ptp *ptp = container_of(ptp_info, struct otx2_ptp,
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ptp_info);
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struct otx2_nic *pfvf = ptp->nic;
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u64 nsec;
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nsec = timespec64_to_ns(ts);
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mutex_lock(&pfvf->mbox.lock);
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timecounter_init(&ptp->time_counter, &ptp->cycle_counter, nsec);
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mutex_unlock(&pfvf->mbox.lock);
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return 0;
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}
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static int otx2_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
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enum ptp_pin_function func, unsigned int chan)
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{
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switch (func) {
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case PTP_PF_NONE:
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case PTP_PF_EXTTS:
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break;
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case PTP_PF_PEROUT:
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case PTP_PF_PHYSYNC:
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return -1;
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}
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return 0;
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}
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static void otx2_ptp_extts_check(struct work_struct *work)
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{
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struct otx2_ptp *ptp = container_of(work, struct otx2_ptp,
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extts_work.work);
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struct ptp_clock_event event;
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u64 tstmp, new_thresh;
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mutex_lock(&ptp->nic->mbox.lock);
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tstmp = ptp_tstmp_read(ptp);
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mutex_unlock(&ptp->nic->mbox.lock);
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if (tstmp != ptp->last_extts) {
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event.type = PTP_CLOCK_EXTTS;
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event.index = 0;
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event.timestamp = timecounter_cyc2time(&ptp->time_counter, tstmp);
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ptp_clock_event(ptp->ptp_clock, &event);
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new_thresh = tstmp % 500000000;
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if (ptp->thresh != new_thresh) {
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mutex_lock(&ptp->nic->mbox.lock);
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ptp_set_thresh(ptp, new_thresh);
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mutex_unlock(&ptp->nic->mbox.lock);
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ptp->thresh = new_thresh;
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}
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ptp->last_extts = tstmp;
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}
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schedule_delayed_work(&ptp->extts_work, msecs_to_jiffies(200));
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}
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static void otx2_sync_tstamp(struct work_struct *work)
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{
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struct otx2_ptp *ptp = container_of(work, struct otx2_ptp,
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synctstamp_work.work);
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struct otx2_nic *pfvf = ptp->nic;
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u64 tstamp;
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mutex_lock(&pfvf->mbox.lock);
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tstamp = otx2_ptp_get_clock(ptp);
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mutex_unlock(&pfvf->mbox.lock);
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ptp->tstamp = timecounter_cyc2time(&pfvf->ptp->time_counter, tstamp);
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ptp->base_ns = tstamp % NSEC_PER_SEC;
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schedule_delayed_work(&ptp->synctstamp_work, msecs_to_jiffies(250));
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}
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static int otx2_ptp_enable(struct ptp_clock_info *ptp_info,
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struct ptp_clock_request *rq, int on)
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{
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struct otx2_ptp *ptp = container_of(ptp_info, struct otx2_ptp,
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ptp_info);
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int pin;
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if (!ptp->nic)
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return -ENODEV;
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switch (rq->type) {
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case PTP_CLK_REQ_EXTTS:
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pin = ptp_find_pin(ptp->ptp_clock, PTP_PF_EXTTS,
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rq->extts.index);
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if (pin < 0)
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return -EBUSY;
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if (on) {
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ptp_extts_on(ptp, on);
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schedule_delayed_work(&ptp->extts_work, msecs_to_jiffies(200));
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} else {
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ptp_extts_on(ptp, on);
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cancel_delayed_work_sync(&ptp->extts_work);
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}
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return 0;
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default:
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break;
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}
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return -EOPNOTSUPP;
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}
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int otx2_ptp_init(struct otx2_nic *pfvf)
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{
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struct otx2_ptp *ptp_ptr;
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struct cyclecounter *cc;
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struct ptp_req *req;
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int err;
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if (is_otx2_lbkvf(pfvf->pdev)) {
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pfvf->ptp = NULL;
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return 0;
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}
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mutex_lock(&pfvf->mbox.lock);
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/* check if PTP block is available */
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req = otx2_mbox_alloc_msg_ptp_op(&pfvf->mbox);
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if (!req) {
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mutex_unlock(&pfvf->mbox.lock);
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return -ENOMEM;
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}
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req->op = PTP_OP_GET_CLOCK;
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err = otx2_sync_mbox_msg(&pfvf->mbox);
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if (err) {
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mutex_unlock(&pfvf->mbox.lock);
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return err;
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}
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mutex_unlock(&pfvf->mbox.lock);
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ptp_ptr = kzalloc(sizeof(*ptp_ptr), GFP_KERNEL);
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if (!ptp_ptr) {
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err = -ENOMEM;
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goto error;
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}
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ptp_ptr->nic = pfvf;
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cc = &ptp_ptr->cycle_counter;
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cc->read = ptp_cc_read;
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cc->mask = CYCLECOUNTER_MASK(64);
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cc->mult = 1;
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cc->shift = 0;
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timecounter_init(&ptp_ptr->time_counter, &ptp_ptr->cycle_counter,
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ktime_to_ns(ktime_get_real()));
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snprintf(ptp_ptr->extts_config.name, sizeof(ptp_ptr->extts_config.name), "TSTAMP");
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ptp_ptr->extts_config.index = 0;
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ptp_ptr->extts_config.func = PTP_PF_NONE;
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ptp_ptr->ptp_info = (struct ptp_clock_info) {
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.owner = THIS_MODULE,
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.name = "OcteonTX2 PTP",
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.max_adj = 1000000000ull,
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.n_ext_ts = 1,
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.n_pins = 1,
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.pps = 0,
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.pin_config = &ptp_ptr->extts_config,
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.adjfine = otx2_ptp_adjfine,
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.adjtime = otx2_ptp_adjtime,
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.gettime64 = otx2_ptp_gettime,
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.settime64 = otx2_ptp_settime,
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.enable = otx2_ptp_enable,
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.verify = otx2_ptp_verify_pin,
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};
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INIT_DELAYED_WORK(&ptp_ptr->extts_work, otx2_ptp_extts_check);
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ptp_ptr->ptp_clock = ptp_clock_register(&ptp_ptr->ptp_info, pfvf->dev);
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if (IS_ERR_OR_NULL(ptp_ptr->ptp_clock)) {
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err = ptp_ptr->ptp_clock ?
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PTR_ERR(ptp_ptr->ptp_clock) : -ENODEV;
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kfree(ptp_ptr);
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goto error;
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}
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if (is_dev_otx2(pfvf->pdev)) {
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ptp_ptr->convert_rx_ptp_tstmp = &otx2_ptp_convert_rx_timestamp;
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ptp_ptr->convert_tx_ptp_tstmp = &otx2_ptp_convert_tx_timestamp;
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} else {
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ptp_ptr->convert_rx_ptp_tstmp = &cn10k_ptp_convert_timestamp;
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ptp_ptr->convert_tx_ptp_tstmp = &cn10k_ptp_convert_timestamp;
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}
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INIT_DELAYED_WORK(&ptp_ptr->synctstamp_work, otx2_sync_tstamp);
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pfvf->ptp = ptp_ptr;
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error:
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return err;
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}
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EXPORT_SYMBOL_GPL(otx2_ptp_init);
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void otx2_ptp_destroy(struct otx2_nic *pfvf)
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{
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struct otx2_ptp *ptp = pfvf->ptp;
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if (!ptp)
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return;
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cancel_delayed_work(&pfvf->ptp->synctstamp_work);
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ptp_clock_unregister(ptp->ptp_clock);
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kfree(ptp);
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pfvf->ptp = NULL;
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}
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EXPORT_SYMBOL_GPL(otx2_ptp_destroy);
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int otx2_ptp_clock_index(struct otx2_nic *pfvf)
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{
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if (!pfvf->ptp)
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return -ENODEV;
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return ptp_clock_index(pfvf->ptp->ptp_clock);
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}
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EXPORT_SYMBOL_GPL(otx2_ptp_clock_index);
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int otx2_ptp_tstamp2time(struct otx2_nic *pfvf, u64 tstamp, u64 *tsns)
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{
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if (!pfvf->ptp)
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return -ENODEV;
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*tsns = timecounter_cyc2time(&pfvf->ptp->time_counter, tstamp);
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return 0;
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}
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EXPORT_SYMBOL_GPL(otx2_ptp_tstamp2time);
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MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>");
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MODULE_DESCRIPTION("Marvell RVU NIC PTP Driver");
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MODULE_LICENSE("GPL v2");
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