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0bdf0621f8
Pull irq subsystem updates from Ingo Molnar: - Add support for the IA55 interrupt controller on RZ/G3S SoC's - Update/fix the Qualcom MPM Interrupt Controller driver's register enumeration within the somewhat exotic "RPM Message RAM" MMIO-mapped shared memory region that is used for other purposes as well - Clean up the Xtensa built-in Programmable Interrupt Controller driver (xtensa-pic) a bit * tag 'irq-core-2024-01-08' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip/irq-xtensa-pic: Clean up irqchip/qcom-mpm: Support passing a slice of SRAM as reg space dt-bindings: interrupt-controller: mpm: Pass MSG RAM slice through phandle dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S irqchip/renesas-rzg2l: Add support for suspend to RAM irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset based on register's index irqchip/renesas-rzg2l: Implement restriction when writing ISCR register irqchip/renesas-rzg2l: Document structure members irqchip/renesas-rzg2l: Align struct member names to tabs irqchip/renesas-rzg2l: Use tabs instead of spaces
119 lines
3.1 KiB
YAML
119 lines
3.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/qcom,mpm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcom MPM Interrupt Controller
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maintainers:
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- Shawn Guo <shawn.guo@linaro.org>
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description:
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Qualcomm Technologies Inc. SoCs based on the RPM architecture have a
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MSM Power Manager (MPM) that is in always-on domain. In addition to managing
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resources during sleep, the hardware also has an interrupt controller that
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monitors the interrupts when the system is asleep, wakes up the APSS when
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one of these interrupts occur and replays it to GIC interrupt controller
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after GIC becomes operational.
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allOf:
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- $ref: /schemas/interrupt-controller.yaml#
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properties:
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compatible:
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items:
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- const: qcom,mpm
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reg:
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maxItems: 1
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description:
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Specifies the base address and size of vMPM registers in RPM MSG RAM.
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deprecated: true
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qcom,rpm-msg-ram:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to the APSS MPM slice of the RPM Message RAM
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interrupts:
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maxItems: 1
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description:
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Specify the IRQ used by RPM to wakeup APSS.
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mboxes:
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maxItems: 1
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description:
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Specify the mailbox used to notify RPM for writing vMPM registers.
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interrupt-controller: true
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'#interrupt-cells':
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const: 2
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description:
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The first cell is the MPM pin number for the interrupt, and the second
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is the trigger type.
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qcom,mpm-pin-count:
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description:
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Specify the total MPM pin count that a SoC supports.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,mpm-pin-map:
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description:
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A set of MPM pin numbers and the corresponding GIC SPIs.
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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items:
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items:
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- description: MPM pin number
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- description: GIC SPI number for the MPM pin
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'#power-domain-cells':
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const: 0
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required:
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- compatible
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- interrupts
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- mboxes
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- interrupt-controller
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- '#interrupt-cells'
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- qcom,mpm-pin-count
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- qcom,mpm-pin-map
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- qcom,rpm-msg-ram
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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remoteproc-rpm {
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compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc";
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glink-edge {
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compatible = "qcom,glink-rpm";
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interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
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qcom,rpm-msg-ram = <&rpm_msg_ram>;
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mboxes = <&apcs_glb 0>;
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};
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mpm: interrupt-controller {
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compatible = "qcom,mpm";
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qcom,rpm-msg-ram = <&apss_mpm>;
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interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
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mboxes = <&apcs_glb 1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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qcom,mpm-pin-count = <96>;
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qcom,mpm-pin-map = <2 275>,
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<5 296>,
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<12 422>,
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<24 79>,
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<86 183>,
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<91 260>;
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#power-domain-cells = <0>;
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};
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};
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