Samuel Holland d6dcdabafc riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 ...

Implementations affected by SiFive errata CIP-1200 have a bug which
forces the kernel to always use the global variant of the sfence.vma
instruction. When affected by this errata, do not attempt to flush a
range of addresses; each iteration of the loop would actually flush the
whole TLB instead. Instead, minimize the overall number of sfence.vma
instructions.

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Yunhui Cui <cuiyunhui@bytedance.com>
Link: https://lore.kernel.org/r/20240327045035.368512-9-samuel.holland@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

2024-04-29 10:49:31 -07:00

..

errata_cip_453.S

riscv: sifive: Apply errata "cip-453" patch

2021-04-26 08:24:57 -07:00

errata.c

riscv: Avoid TLB flush loops when affected by SiFive CIP-1200

2024-04-29 10:49:31 -07:00

Makefile

riscv: skip errata_cip_453.o if CONFIG_ERRATA_SIFIVE_CIP_453 is disabled

2021-06-01 21:16:41 -07:00