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06db7fded6
Exposes a bunch of the new features that became possible as a result
of the earlier commits. DRM will build on this in the future to add
support for features such as SCG ("async compute") and multi-device
rendering, as part of the work necessary to be able to write a half-
decent vulkan driver - finally.
For the moment, this just crudely ports DRM to the API changes.
- channel class interfaces now the same for all HW classes
- channel group class exposed (SCG)
- channel runqueue selector exposed (SCG)
- channel sub-device id control exposed (multi-device rendering)
- channel names in logging will reflect creating process, not fd owner
- explicit USERD allocation required by VOLTA_CHANNEL_GPFIFO_A and newer
- drm is smarter about determining the appropriate channel class to use
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
46 lines
791 B
C
46 lines
791 B
C
/* SPDX-License-Identifier: MIT */
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#ifndef __NVIF_IF0020_H__
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#define __NVIF_IF0020_H__
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union nvif_chan_args {
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struct nvif_chan_v0 {
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__u8 version;
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__u8 namelen;
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__u8 runlist;
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__u8 runq;
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__u8 priv;
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__u8 pad05;
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__u16 devm;
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__u64 vmm;
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__u64 ctxdma;
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__u64 offset;
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__u64 length;
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__u64 huserd;
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__u64 ouserd;
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__u32 token;
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__u16 chid;
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__u8 pad3e;
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#define NVIF_CHAN_V0_INST_APER_VRAM 0
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#define NVIF_CHAN_V0_INST_APER_HOST 1
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#define NVIF_CHAN_V0_INST_APER_NCOH 2
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#define NVIF_CHAN_V0_INST_APER_INST 0xff
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__u8 aper;
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__u64 inst;
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__u8 name[];
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} v0;
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};
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union nvif_chan_event_args {
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struct nvif_chan_event_v0 {
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__u8 version;
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#define NVIF_CHAN_EVENT_V0_NON_STALL_INTR 0x00
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#define NVIF_CHAN_EVENT_V0_KILLED 0x01
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__u8 type;
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} v0;
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};
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#endif
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