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[Why] Some of the stream encoder registers have register offset address 0. It is causing no display in some scenarios due to DIG_FE was not setup correctly and was not enabled. [How] Fix stream encoder register define list. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Duncan Ma <duncan.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>