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bf74bb73cd
Currently, LPA2 kernel support implies support for up to 52 bits of
physical addressing, and this is reflected in global definitions such as
PHYS_MASK_SHIFT and MAX_PHYSMEM_BITS.
This is potentially problematic, given that LPA2 hardware support is
modeled as a CPU feature which can be overridden, and with LPA2 hardware
support turned off, attempting to map physical regions with address bits
[51:48] set (which may exist on LPA2 capable systems booting with
arm64.nolva) will result in corrupted mappings with a truncated output
address and bogus shareability attributes.
This means that the accepted physical address range in the mapping
routines should be at most 48 bits wide when LPA2 support is configured
but not enabled at runtime.
Fixes: 352b0395b5 ("arm64: Enable 52-bit virtual addressing for 4k and 16k granule configs")
Cc: stable@vger.kernel.org
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Acked-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20241212081841.2168124-9-ardb+git@google.com
Signed-off-by: Will Deacon <will@kernel.org>
194 lines
8.2 KiB
C
194 lines
8.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2016 ARM Ltd.
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*/
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#ifndef __ASM_PGTABLE_PROT_H
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#define __ASM_PGTABLE_PROT_H
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#include <asm/memory.h>
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#include <asm/pgtable-hwdef.h>
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#include <linux/const.h>
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/*
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* Software defined PTE bits definition.
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*/
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#define PTE_WRITE (PTE_DBM) /* same as DBM (51) */
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#define PTE_SWP_EXCLUSIVE (_AT(pteval_t, 1) << 2) /* only for swp ptes */
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#define PTE_DIRTY (_AT(pteval_t, 1) << 55)
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#define PTE_SPECIAL (_AT(pteval_t, 1) << 56)
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#define PTE_DEVMAP (_AT(pteval_t, 1) << 57)
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/*
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* PTE_PRESENT_INVALID=1 & PTE_VALID=0 indicates that the pte's fields should be
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* interpreted according to the HW layout by SW but any attempted HW access to
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* the address will result in a fault. pte_present() returns true.
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*/
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#define PTE_PRESENT_INVALID (PTE_NG) /* only when !PTE_VALID */
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#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
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#define PTE_UFFD_WP (_AT(pteval_t, 1) << 58) /* uffd-wp tracking */
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#define PTE_SWP_UFFD_WP (_AT(pteval_t, 1) << 3) /* only for swp ptes */
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#else
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#define PTE_UFFD_WP (_AT(pteval_t, 0))
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#define PTE_SWP_UFFD_WP (_AT(pteval_t, 0))
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#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
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#define _PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
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#define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_MAYBE_NG | PTE_MAYBE_SHARED | PTE_AF)
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#define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_MAYBE_NG | PMD_MAYBE_SHARED | PMD_SECT_AF)
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#define PROT_DEVICE_nGnRnE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE))
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#define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE))
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#define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
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#define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
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#define PROT_NORMAL_TAGGED (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_TAGGED))
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#define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
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#define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PTE_WRITE | PMD_ATTRINDX(MT_NORMAL))
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#define PROT_SECT_NORMAL_EXEC (PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
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#define _PAGE_DEFAULT (_PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
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#define _PAGE_KERNEL (PROT_NORMAL)
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#define _PAGE_KERNEL_RO ((PROT_NORMAL & ~PTE_WRITE) | PTE_RDONLY)
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#define _PAGE_KERNEL_ROX ((PROT_NORMAL & ~(PTE_WRITE | PTE_PXN)) | PTE_RDONLY)
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#define _PAGE_KERNEL_EXEC (PROT_NORMAL & ~PTE_PXN)
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#define _PAGE_KERNEL_EXEC_CONT ((PROT_NORMAL & ~PTE_PXN) | PTE_CONT)
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#define _PAGE_SHARED (_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
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#define _PAGE_SHARED_EXEC (_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_WRITE)
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#define _PAGE_READONLY (_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
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#define _PAGE_READONLY_EXEC (_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN)
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#define _PAGE_EXECONLY (_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PTE_PXN)
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#ifndef __ASSEMBLY__
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#include <asm/cpufeature.h>
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#include <asm/pgtable-types.h>
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#include <asm/rsi.h>
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extern bool arm64_use_ng_mappings;
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extern unsigned long prot_ns_shared;
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#define PROT_NS_SHARED (is_realm_world() ? prot_ns_shared : 0)
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#define PTE_MAYBE_NG (arm64_use_ng_mappings ? PTE_NG : 0)
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#define PMD_MAYBE_NG (arm64_use_ng_mappings ? PMD_SECT_NG : 0)
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#ifndef CONFIG_ARM64_LPA2
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#define lpa2_is_enabled() false
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#define PTE_MAYBE_SHARED PTE_SHARED
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#define PMD_MAYBE_SHARED PMD_SECT_S
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#define PHYS_MASK_SHIFT (CONFIG_ARM64_PA_BITS)
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#else
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static inline bool __pure lpa2_is_enabled(void)
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{
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return read_tcr() & TCR_DS;
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}
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#define PTE_MAYBE_SHARED (lpa2_is_enabled() ? 0 : PTE_SHARED)
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#define PMD_MAYBE_SHARED (lpa2_is_enabled() ? 0 : PMD_SECT_S)
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#define PHYS_MASK_SHIFT (lpa2_is_enabled() ? CONFIG_ARM64_PA_BITS : 48)
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#endif
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/*
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* Highest possible physical address supported.
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*/
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#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1)
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/*
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* If we have userspace only BTI we don't want to mark kernel pages
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* guarded even if the system does support BTI.
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*/
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#define PTE_MAYBE_GP (system_supports_bti_kernel() ? PTE_GP : 0)
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#define PAGE_KERNEL __pgprot(_PAGE_KERNEL)
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#define PAGE_KERNEL_RO __pgprot(_PAGE_KERNEL_RO)
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#define PAGE_KERNEL_ROX __pgprot(_PAGE_KERNEL_ROX)
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#define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL_EXEC)
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#define PAGE_KERNEL_EXEC_CONT __pgprot(_PAGE_KERNEL_EXEC_CONT)
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#define PAGE_S2_MEMATTR(attr, has_fwb) \
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({ \
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u64 __val; \
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if (has_fwb) \
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__val = PTE_S2_MEMATTR(MT_S2_FWB_ ## attr); \
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else \
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__val = PTE_S2_MEMATTR(MT_S2_ ## attr); \
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__val; \
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})
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#define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PRESENT_INVALID | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
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/* shared+writable pages are clean by default, hence PTE_RDONLY|PTE_WRITE */
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#define PAGE_SHARED __pgprot(_PAGE_SHARED)
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#define PAGE_SHARED_EXEC __pgprot(_PAGE_SHARED_EXEC)
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#define PAGE_READONLY __pgprot(_PAGE_READONLY)
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#define PAGE_READONLY_EXEC __pgprot(_PAGE_READONLY_EXEC)
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#define PAGE_EXECONLY __pgprot(_PAGE_EXECONLY)
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#endif /* __ASSEMBLY__ */
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#define pte_pi_index(pte) ( \
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((pte & BIT(PTE_PI_IDX_3)) >> (PTE_PI_IDX_3 - 3)) | \
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((pte & BIT(PTE_PI_IDX_2)) >> (PTE_PI_IDX_2 - 2)) | \
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((pte & BIT(PTE_PI_IDX_1)) >> (PTE_PI_IDX_1 - 1)) | \
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((pte & BIT(PTE_PI_IDX_0)) >> (PTE_PI_IDX_0 - 0)))
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/*
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* Page types used via Permission Indirection Extension (PIE). PIE uses
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* the USER, DBM, PXN and UXN bits to to generate an index which is used
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* to look up the actual permission in PIR_ELx and PIRE0_EL1. We define
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* combinations we use on non-PIE systems with the same encoding, for
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* convenience these are listed here as comments as are the unallocated
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* encodings.
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*/
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/* 0: PAGE_DEFAULT */
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/* 1: PTE_USER */
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/* 2: PTE_WRITE */
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/* 3: PTE_WRITE | PTE_USER */
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/* 4: PAGE_EXECONLY PTE_PXN */
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/* 5: PAGE_READONLY_EXEC PTE_PXN | PTE_USER */
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/* 6: PTE_PXN | PTE_WRITE */
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/* 7: PAGE_SHARED_EXEC PTE_PXN | PTE_WRITE | PTE_USER */
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/* 8: PAGE_KERNEL_ROX PTE_UXN */
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/* 9: PAGE_GCS_RO PTE_UXN | PTE_USER */
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/* a: PAGE_KERNEL_EXEC PTE_UXN | PTE_WRITE */
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/* b: PAGE_GCS PTE_UXN | PTE_WRITE | PTE_USER */
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/* c: PAGE_KERNEL_RO PTE_UXN | PTE_PXN */
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/* d: PAGE_READONLY PTE_UXN | PTE_PXN | PTE_USER */
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/* e: PAGE_KERNEL PTE_UXN | PTE_PXN | PTE_WRITE */
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/* f: PAGE_SHARED PTE_UXN | PTE_PXN | PTE_WRITE | PTE_USER */
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#define _PAGE_GCS (_PAGE_DEFAULT | PTE_NG | PTE_UXN | PTE_WRITE | PTE_USER)
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#define _PAGE_GCS_RO (_PAGE_DEFAULT | PTE_NG | PTE_UXN | PTE_USER)
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#define PAGE_GCS __pgprot(_PAGE_GCS)
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#define PAGE_GCS_RO __pgprot(_PAGE_GCS_RO)
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#define PIE_E0 ( \
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PIRx_ELx_PERM(pte_pi_index(_PAGE_GCS), PIE_GCS) | \
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PIRx_ELx_PERM(pte_pi_index(_PAGE_GCS_RO), PIE_R) | \
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PIRx_ELx_PERM(pte_pi_index(_PAGE_EXECONLY), PIE_X_O) | \
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PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY_EXEC), PIE_RX_O) | \
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PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED_EXEC), PIE_RWX_O) | \
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PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY), PIE_R_O) | \
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PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED), PIE_RW_O))
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#define PIE_E1 ( \
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PIRx_ELx_PERM(pte_pi_index(_PAGE_GCS), PIE_NONE_O) | \
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PIRx_ELx_PERM(pte_pi_index(_PAGE_GCS_RO), PIE_NONE_O) | \
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PIRx_ELx_PERM(pte_pi_index(_PAGE_EXECONLY), PIE_NONE_O) | \
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PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY_EXEC), PIE_R) | \
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PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED_EXEC), PIE_RW) | \
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PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY), PIE_R) | \
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PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED), PIE_RW) | \
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PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_ROX), PIE_RX) | \
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PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_EXEC), PIE_RWX) | \
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PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_RO), PIE_R) | \
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PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL), PIE_RW))
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#endif /* __ASM_PGTABLE_PROT_H */
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