Austin Zheng fae0e342f5 drm/amd/display: DML21 Update Prefetch Calculations ...

[Why/How]
Mismatch between mode support and mode programming occurs.
Mode support would calculate higher row vblank than mode programming.
As a result, mode programming fails and hardware isn't properly programmed.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Austin Zheng <Austin.Zheng@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2024-12-10 10:31:52 -05:00

..

acp

drivers/gpu: Fix misalignment in comment block

2024-05-29 14:48:30 -04:00

amdgpu

drm/amdgpu: Support nbif v6_3_1 fatal error handling

2024-12-10 10:31:00 -05:00

amdkfd

drm/amdkfd: update the cwsr area size for gfx950

2024-12-10 10:26:51 -05:00

amdxcp

drm/amd/amdxcp: Fix warnings

2024-05-08 15:17:05 -04:00

display

drm/amd/display: DML21 Update Prefetch Calculations

2024-12-10 10:31:52 -05:00

include

drm/amd: Update atomfirmware: add new retimer definition

2024-12-10 10:29:05 -05:00

pm

drm/amd/pm: Revert state if force level fails

2024-12-10 10:29:55 -05:00