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EDAC/altera: Handle OCRAM ECC enable after warm reset

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commit fd3ecda38f upstream.

The OCRAM ECC is always enabled either by the BootROM or by the Secure Device
Manager (SDM) during a power-on reset on SoCFPGA.

However, during a warm reset, the OCRAM content is retained to preserve data,
while the control and status registers are reset to their default values. As
a result, ECC must be explicitly re-enabled after a warm reset.

Fixes: 17e47dc6db ("EDAC/altera: Add Stratix10 OCRAM ECC support")
Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20251111080801.1279401-1-niravkumarlaxmidas.rabara@altera.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Niravkumar L Rabara
2025-11-11 16:08:01 +08:00
committed by Greg Kroah-Hartman
parent 8e5aa33ef5
commit 0f64b37f19
1 changed files with 15 additions and 3 deletions
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18
drivers/edac/altera_edac.c
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@@ -1184,10 +1184,22 @@ altr_check_ocram_deps_init(struct altr_edac_device_dev *device)
if (ret)
return ret;
/* Verify OCRAM has been initialized */
/*
* Verify that OCRAM has been initialized.
* During a warm reset, OCRAM contents are retained, but the control
* and status registers are reset to their default values. Therefore,
* ECC must be explicitly re-enabled in the control register.
* Error condition: if INITCOMPLETEA is clear and ECC_EN is already set.
*/
if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA,
(base + ALTR_A10_ECC_INITSTAT_OFST)))
return -ENODEV;
(base + ALTR_A10_ECC_INITSTAT_OFST))) {
if (!ecc_test_bits(ALTR_A10_ECC_EN,
(base + ALTR_A10_ECC_CTRL_OFST)))
ecc_set_bits(ALTR_A10_ECC_EN,
(base + ALTR_A10_ECC_CTRL_OFST));
else
return -ENODEV;
}
/* Enable IRQ on Single Bit Error */
writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST));