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https://github.com/raspberrypi/linux.git
synced 2025-12-06 01:49:46 +00:00
drivers: mmc: add SD support for Command Queueing
Application class A2 cards require CQ to be enabled to realise their stated performance figures. Add support to enable/disable card CQ via the Performance Enhancement extension register, and cater for the slight differences in command set versus eMMC. Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
This commit is contained in:
committed by
Dom Cobley
parent
125a9b0c16
commit
1379718b89
@@ -896,7 +896,10 @@ static int mmc_blk_part_switch_pre(struct mmc_card *card,
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if ((part_type & mask) == rpmb) {
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if (card->ext_csd.cmdq_en) {
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ret = mmc_cmdq_disable(card);
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if (mmc_card_sd(card))
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ret = mmc_sd_cmdq_disable(card);
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else
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ret = mmc_cmdq_disable(card);
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if (ret)
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return ret;
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}
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@@ -915,8 +918,12 @@ static int mmc_blk_part_switch_post(struct mmc_card *card,
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if ((part_type & mask) == rpmb) {
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mmc_retune_unpause(card->host);
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if (card->reenable_cmdq && !card->ext_csd.cmdq_en)
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ret = mmc_cmdq_enable(card);
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if (card->reenable_cmdq && !card->ext_csd.cmdq_en) {
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if (mmc_card_sd(card))
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ret = mmc_sd_cmdq_enable(card);
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else
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ret = mmc_cmdq_enable(card);
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}
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}
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return ret;
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@@ -1127,7 +1134,10 @@ static void mmc_blk_issue_drv_op(struct mmc_queue *mq, struct request *req)
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switch (mq_rq->drv_op) {
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case MMC_DRV_OP_IOCTL:
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if (card->ext_csd.cmdq_en) {
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ret = mmc_cmdq_disable(card);
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if (mmc_card_sd(card))
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ret = mmc_sd_cmdq_disable(card);
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else
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ret = mmc_cmdq_disable(card);
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if (ret)
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break;
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}
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@@ -1145,8 +1155,12 @@ static void mmc_blk_issue_drv_op(struct mmc_queue *mq, struct request *req)
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/* Always switch back to main area after RPMB access */
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if (rpmb_ioctl)
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mmc_blk_part_switch(card, 0);
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else if (card->reenable_cmdq && !card->ext_csd.cmdq_en)
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mmc_cmdq_enable(card);
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else if (card->reenable_cmdq && !card->ext_csd.cmdq_en) {
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if (mmc_card_sd(card))
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mmc_sd_cmdq_enable(card);
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else
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mmc_cmdq_enable(card);
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}
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break;
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case MMC_DRV_OP_BOOT_WP:
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ret = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_WP,
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@@ -563,7 +563,11 @@ int mmc_cqe_recovery(struct mmc_host *host)
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mmc_poll_for_busy(host->card, MMC_CQE_RECOVERY_TIMEOUT, true, MMC_BUSY_IO);
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memset(&cmd, 0, sizeof(cmd));
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cmd.opcode = MMC_CMDQ_TASK_MGMT;
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if (mmc_card_sd(host->card))
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cmd.opcode = SD_CMDQ_TASK_MGMT;
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else
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cmd.opcode = MMC_CMDQ_TASK_MGMT;
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cmd.arg = 1; /* Discard entire queue */
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cmd.flags = MMC_RSP_R1B_NO_CRC | MMC_CMD_AC; /* Ignore CRC */
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cmd.busy_timeout = MMC_CQE_RECOVERY_TIMEOUT;
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@@ -1034,8 +1034,8 @@ static bool mmc_sd_card_using_v18(struct mmc_card *card)
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(SD_MODE_UHS_SDR50 | SD_MODE_UHS_SDR104 | SD_MODE_UHS_DDR50);
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}
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static int sd_write_ext_reg(struct mmc_card *card, u8 fno, u8 page, u16 offset,
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u8 reg_data)
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int sd_write_ext_reg(struct mmc_card *card, u8 fno, u8 page, u16 offset,
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u8 reg_data)
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{
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struct mmc_host *host = card->host;
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struct mmc_request mrq = {};
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@@ -1193,8 +1193,14 @@ static int sd_parse_ext_reg_perf(struct mmc_card *card, u8 fno, u8 page,
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card->ext_perf.feature_support |= SD_EXT_PERF_CACHE;
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/* Command queue support indicated via queue depth bits (0 to 4). */
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if (reg_buf[6] & 0x1f)
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if (reg_buf[6] & 0x1f) {
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card->ext_perf.feature_support |= SD_EXT_PERF_CMD_QUEUE;
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card->ext_csd.cmdq_depth = reg_buf[6] & 0x1f;
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card->ext_csd.cmdq_support = true;
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pr_debug("%s: Command Queue supported depth %u\n",
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mmc_hostname(card->host),
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card->ext_csd.cmdq_depth);
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}
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card->ext_perf.fno = fno;
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card->ext_perf.page = page;
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@@ -1584,13 +1590,41 @@ cont:
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goto free_card;
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}
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/* Enable command queueing if supported */
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if (card->ext_csd.cmdq_support && host->caps2 & MMC_CAP2_CQE) {
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/*
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* Right now the MMC block layer uses DCMDs to issue
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* cache-flush commands specific to eMMC devices.
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* Turning off DCMD support avoids generating Illegal Command
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* errors on SD, and flushing is instead done synchronously
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* by mmc_blk_issue_flush().
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*/
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host->caps2 &= ~MMC_CAP2_CQE_DCMD;
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err = mmc_sd_cmdq_enable(card);
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if (err && err != -EBADMSG)
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goto free_card;
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if (err) {
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pr_warn("%s: Enabling CMDQ failed\n",
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mmc_hostname(card->host));
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card->ext_csd.cmdq_support = false;
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card->ext_csd.cmdq_depth = 0;
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}
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}
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card->reenable_cmdq = card->ext_csd.cmdq_en;
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if (!mmc_card_ult_capacity(card) && host->cqe_ops && !host->cqe_enabled) {
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err = host->cqe_ops->cqe_enable(host, card);
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if (!err) {
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host->cqe_enabled = true;
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host->hsq_enabled = true;
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pr_info("%s: Host Software Queue enabled\n",
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mmc_hostname(host));
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if (card->ext_csd.cmdq_en) {
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pr_info("%s: Command Queue Engine enabled\n",
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mmc_hostname(host));
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} else {
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host->hsq_enabled = true;
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pr_info("%s: Host Software Queue enabled\n",
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mmc_hostname(host));
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}
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}
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}
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@@ -417,3 +417,40 @@ int mmc_app_sd_status(struct mmc_card *card, void *ssr)
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return 0;
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}
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int sd_write_ext_reg(struct mmc_card *card, u8 fno, u8 page, u16 offset,
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u8 reg_data);
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static int mmc_sd_cmdq_switch(struct mmc_card *card, bool enable)
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{
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int err;
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u8 reg = 0;
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/*
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* SD offers two command queueing modes - sequential (in-order) and
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* voluntary (out-of-order). Apps Class A2 performance is only
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* guaranteed for voluntary CQ (bit 1 = 0), so use that in preference
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* to sequential.
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*/
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if (enable)
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reg = BIT(0);
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/* Performance enhancement register byte 262 controls command queueing */
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err = sd_write_ext_reg(card, card->ext_perf.fno, card->ext_perf.page,
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card->ext_perf.offset + 262, reg);
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if (!err)
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card->ext_csd.cmdq_en = enable;
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return err;
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}
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int mmc_sd_cmdq_enable(struct mmc_card *card)
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{
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return mmc_sd_cmdq_switch(card, true);
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}
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EXPORT_SYMBOL_GPL(mmc_sd_cmdq_enable);
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int mmc_sd_cmdq_disable(struct mmc_card *card)
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{
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return mmc_sd_cmdq_switch(card, false);
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}
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EXPORT_SYMBOL_GPL(mmc_sd_cmdq_disable);
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@@ -24,6 +24,8 @@ int mmc_app_sd_status(struct mmc_card *card, void *ssr);
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int mmc_app_cmd(struct mmc_host *host, struct mmc_card *card);
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int mmc_send_ext_addr(struct mmc_host *host, u32 addr);
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void mmc_uhs2_prepare_cmd(struct mmc_host *host, struct mmc_request *mrq);
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int mmc_sd_cmdq_enable(struct mmc_card *card);
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int mmc_sd_cmdq_disable(struct mmc_card *card);
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#endif
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@@ -32,6 +32,9 @@
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#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */
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#define SD_APP_SEND_SCR 51 /* adtc R1 */
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/* class 1 */
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#define SD_CMDQ_TASK_MGMT 43 /* ac See below R1b */
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/* class 11 */
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#define SD_READ_EXTR_SINGLE 48 /* adtc [31:0] R1 */
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#define SD_WRITE_EXTR_SINGLE 49 /* adtc [31:0] R1 */
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@@ -64,6 +67,15 @@
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* [7:0] Check Pattern (0xAA)
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*/
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/*
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* SD_CMDQ_TASK_MGMT argument format:
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*
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* [31:21] Reserved (0)
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* [20:16] Task ID
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* [15:4] Reserved (0)
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* [3:0] Operation - 0x1 = abort all tasks, 0x2 = abort Task ID
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*/
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/*
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* SCR field definitions
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*/
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