raspi/linux
1
0
Fork 1
mirror of https://github.com/raspberrypi/linux.git synced 2025-12-06 01:49:46 +00:00
Code Issues Projects Releases Wiki Activity

drm/vc4: Fixup mode for 7inch panel on DSI0

Browse Source 
The TC358762 bridge and panel decodes the mode differently on
DSI0 to DSI1 for no obvious reason, and results in a shift off
the screen.
Whilst it would be possible to change the compatible used for
the panel, that then messes up Pi5.

As it appears to be restricted to vc4 DSI0, fix up the mode
in vc4_dsi.

Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
This commit is contained in:
Dave Stevenson
2024-04-26 17:48:06 +01:00
committed by Dom Cobley
parent df24a7357f
commit 6c9aee1797
1 changed files with 19 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
drivers/gpu/drm/vc4/vc4_dsi.c
View File

@@ -869,6 +869,7 @@ static bool vc4_dsi_bridge_mode_fixup(struct drm_bridge *bridge,
unsigned long pixel_clock_hz = mode->clock * 1000;
unsigned long pll_clock = pixel_clock_hz * dsi->divider;
int divider;
u16 htotal;
/* Find what divider gets us a faster clock than the requested
* pixel clock.
@@ -885,12 +886,27 @@ static bool vc4_dsi_bridge_mode_fixup(struct drm_bridge *bridge,
pixel_clock_hz = pll_clock / dsi->divider;
adjusted_mode->clock = pixel_clock_hz / 1000;
htotal = mode->htotal;
if (dsi->variant->port == 0 && mode->clock == 30000 &&
mode->hdisplay == 800 && mode->htotal == (800 + 59 + 2 + 45) &&
mode->vdisplay == 480 && mode->vtotal == (480 + 7 + 2 + 22)) {
/*
* Raspberry Pi 7" panel via TC358762 seems to have an issue on
* DSI0 that it doesn't actually follow the vertical timing that
* is otherwise identical to that produced on DSI1.
* Fixup the mode.
*/
htotal = 800 + 59 + 2 + 47;
adjusted_mode->vtotal = 480 + 7 + 2 + 45;
adjusted_mode->crtc_vtotal = 480 + 7 + 2 + 45;
}
/* Given the new pixel clock, adjust HFP to keep vrefresh the same. */
adjusted_mode->htotal = adjusted_mode->clock * mode->htotal /
adjusted_mode->htotal = adjusted_mode->clock * htotal /
mode->clock;
adjusted_mode->hsync_end += adjusted_mode->htotal - mode->htotal;
adjusted_mode->hsync_start += adjusted_mode->htotal - mode->htotal;
adjusted_mode->hsync_end += adjusted_mode->htotal - htotal;
adjusted_mode->hsync_start += adjusted_mode->htotal - htotal;
return true;
}