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Revert "drm/xe: Force write completion of MI_STORE_DATA_IMM"

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This reverts commit 1460bb1fef.

In all places the MI_STORE_DATA_IMM are not followed by a read of
the same memory address in the same batch buffer and the posted writes
are flushed with PIPE_CONTROL or MI_FLUSH_DW in xe_ring_ops.c functions
so there is no need to set this register.

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Fixes: 1460bb1fef ("drm/xe: Force write completion of MI_STORE_DATA_IMM")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241227183230.101334-1-jose.souza@intel.com
This commit is contained in:
José Roberto de Souza
2024-12-27 10:32:19 -08:00
parent fba0f039af
commit 88fca61ba5
3 changed files with 11 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/gpu/drm/xe/instructions/xe_mi_commands.h
View File

@@ -33,13 +33,12 @@
#define MI_TOPOLOGY_FILTER __MI_INSTR(0xD)
#define MI_FORCE_WAKEUP __MI_INSTR(0x1D)
#define MI_STORE_DATA_IMM __MI_INSTR(0x20)
#define MI_SDI_GGTT REG_BIT(22)
#define MI_FORCE_WRITE_COMPLETION_CHECK REG_BIT(10)
#define MI_SDI_LEN_DW GENMASK(9, 0)
#define MI_SDI_NUM_DW(x) REG_FIELD_PREP(MI_SDI_LEN_DW, (x) + 3 - 2)
#define MI_SDI_NUM_QW(x) (REG_FIELD_PREP(MI_SDI_LEN_DW, 2 * (x) + 3 - 2) | \
REG_BIT(21))
#define MI_STORE_DATA_IMM __MI_INSTR(0x20)
#define MI_SDI_GGTT REG_BIT(22)
#define MI_SDI_LEN_DW GENMASK(9, 0)
#define MI_SDI_NUM_DW(x) REG_FIELD_PREP(MI_SDI_LEN_DW, (x) + 3 - 2)
#define MI_SDI_NUM_QW(x) (REG_FIELD_PREP(MI_SDI_LEN_DW, 2 * (x) + 3 - 2) | \
REG_BIT(21))
#define MI_LOAD_REGISTER_IMM __MI_INSTR(0x22)
#define MI_LRI_LRM_CS_MMIO REG_BIT(19)

11
drivers/gpu/drm/xe/xe_migrate.c
View File

@@ -581,9 +581,7 @@ static void emit_pte(struct xe_migrate *m,
while (ptes) {
u32 chunk = min(MAX_PTE_PER_SDI, ptes);
bb->cs[bb->len++] = MI_STORE_DATA_IMM |
MI_FORCE_WRITE_COMPLETION_CHECK |
MI_SDI_NUM_QW(chunk);
bb->cs[bb->len++] = MI_STORE_DATA_IMM | MI_SDI_NUM_QW(chunk);
bb->cs[bb->len++] = ofs;
bb->cs[bb->len++] = 0;
@@ -1225,9 +1223,7 @@ static void write_pgtable(struct xe_tile *tile, struct xe_bb *bb, u64 ppgtt_ofs,
if (!(bb->len & 1))
bb->cs[bb->len++] = MI_NOOP;
bb->cs[bb->len++] = MI_STORE_DATA_IMM |
MI_FORCE_WRITE_COMPLETION_CHECK |
MI_SDI_NUM_QW(chunk);
bb->cs[bb->len++] = MI_STORE_DATA_IMM | MI_SDI_NUM_QW(chunk);
bb->cs[bb->len++] = lower_32_bits(addr);
bb->cs[bb->len++] = upper_32_bits(addr);
if (pt_op->bind)
@@ -1392,8 +1388,7 @@ __xe_migrate_update_pgtables(struct xe_migrate *m,
u32 idx = 0;
bb->cs[bb->len++] = MI_STORE_DATA_IMM |
MI_FORCE_WRITE_COMPLETION_CHECK |
MI_SDI_NUM_QW(chunk);
MI_SDI_NUM_QW(chunk);
bb->cs[bb->len++] = ofs;
bb->cs[bb->len++] = 0; /* upper_32_bits */

6
drivers/gpu/drm/xe/xe_ring_ops.c
View File

@@ -72,8 +72,7 @@ static int emit_user_interrupt(u32 *dw, int i)
static int emit_store_imm_ggtt(u32 addr, u32 value, u32 *dw, int i)
{
dw[i++] = MI_STORE_DATA_IMM | MI_SDI_GGTT |
MI_FORCE_WRITE_COMPLETION_CHECK | MI_SDI_NUM_DW(1);
dw[i++] = MI_STORE_DATA_IMM | MI_SDI_GGTT | MI_SDI_NUM_DW(1);
dw[i++] = addr;
dw[i++] = 0;
dw[i++] = value;
@@ -163,8 +162,7 @@ static int emit_pipe_invalidate(u32 mask_flags, bool invalidate_tlb, u32 *dw,
static int emit_store_imm_ppgtt_posted(u64 addr, u64 value,
u32 *dw, int i)
{
dw[i++] = MI_STORE_DATA_IMM | MI_FORCE_WRITE_COMPLETION_CHECK |
MI_SDI_NUM_QW(1);
dw[i++] = MI_STORE_DATA_IMM | MI_SDI_NUM_QW(1);
dw[i++] = lower_32_bits(addr);
dw[i++] = upper_32_bits(addr);
dw[i++] = lower_32_bits(value);