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drm/xe: Add mmio read before GGTT invalidate
On LNL without a mmio read before a GGTT invalidate the GuC can incorrectly read the GGTT scratch page upon next access leading to jobs not getting scheduled. A mmio read before a GGTT invalidate seems to fix this. Since a GGTT invalidate is not a hot code path, blindly do a mmio read before each GGTT invalidate. Cc: John Harrison <John.C.Harrison@Intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: stable@vger.kernel.org Fixes:dd08ebf6c3("drm/xe: Introduce a new DRM driver for Intel GPUs") Reported-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/3164 Signed-off-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241023221200.1797832-1-matthew.brost@intel.com Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> (cherry picked from commit5a71019688) [ Fix conflict with mmio vs gt argument ] Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
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committed by
Lucas De Marchi
parent
6a9d2e2988
commit
993ca0ecce
@@ -397,6 +397,16 @@ static void ggtt_invalidate_gt_tlb(struct xe_gt *gt)
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static void xe_ggtt_invalidate(struct xe_ggtt *ggtt)
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{
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struct xe_device *xe = tile_to_xe(ggtt->tile);
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/*
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* XXX: Barrier for GGTT pages. Unsure exactly why this required but
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* without this LNL is having issues with the GuC reading scratch page
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* vs. correct GGTT page. Not particularly a hot code path so blindly
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* do a mmio read here which results in GuC reading correct GGTT page.
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*/
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xe_mmio_read32(xe_root_mmio_gt(xe), VF_CAP_REG);
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/* Each GT in a tile has its own TLB to cache GGTT lookups */
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ggtt_invalidate_gt_tlb(ggtt->tile->primary_gt);
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ggtt_invalidate_gt_tlb(ggtt->tile->media_gt);
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