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riscv: dts: allwinner: d1: fix vlenb property

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According to [1], the C906 vector registers are 128 bits wide.
The 'thead,vlenb' property specifies the vector register length
in bytes, so its value must be set to 16.

[1] https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf

Fixes: ce1daeeba6 ("riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree")
Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
Link: https://patch.msgid.link/20251119203508.1032716-1-geomatsi@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
This commit is contained in:
Sergey Matyukevich
2025-11-19 23:35:06 +03:00
committed by Chen-Yu Tsai
parent 3a86608788
commit 9f393d8e75
1 changed files with 1 additions and 1 deletions
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arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
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@@ -28,7 +28,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm", "xtheadvector";
thead,vlenb = <128>;
thead,vlenb = <16>;
#cooling-cells = <2>;
cpu0_intc: interrupt-controller {