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PCI: quirks: work around VL805 firmware ASPM meddling

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Certain versions of the VL805 firmware manipulate the endpoint Link
Control register to toggle ASPM on/off based on workload, but these
versions also report 0 in the Device Capability Acceptable Latency field
leaving the RC with ASPM disabled.

As it turns out, this EP has a broken L0s implementation so a) override
L1 latency to a sensible value and b) mask L0s.

Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
This commit is contained in:
Jonathan Bell
2025-04-15 14:19:31 +01:00
committed by Dom Cobley
parent 5bc8271fe5
commit b4b55534f1
1 changed files with 16 additions and 0 deletions
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16
drivers/pci/quirks.c
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@@ -6249,6 +6249,22 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b0, aspm_l1_acceptable_latency
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency);
/*
* VL805 firmware can report 0 in the L0s/L1 Acceptable Latency fields.
* This is shorter than its own exit latency so ASPM for the link partner
* never gets enabled (but firmware toggles EP L1/L0s enable internally).
* However, L0s is flaky so explicitly disable it.
*/
static void vl805_aspm_fixup(struct pci_dev *dev)
{
dev->devcap &= ~PCI_EXP_DEVCAP_L1;
/* Set to own exit latency + 1 */
dev->devcap |= FIELD_PREP(PCI_EXP_DEVCAP_L1, 5);
pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
pci_info(dev, "ASPM: VL805 fixup applied\n");
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, 0x3483, vl805_aspm_fixup);
#endif
#ifdef CONFIG_PCIE_DPC