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drm/amd/pm: Disable MCLK switching on SI at high pixel clocks

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[ Upstream commit 5c05bcf6ae ]

On various SI GPUs, a flickering can be observed near the bottom
edge of the screen when using a single 4K 60Hz monitor over DP.
Disabling MCLK switching works around this problem.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Timur Kristóf
2025-09-26 20:26:12 +02:00
committed by Greg Kroah-Hartman
parent eaf12bffd7
commit d033e8cf4e
1 changed files with 5 additions and 0 deletions
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5
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
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@@ -3485,6 +3485,11 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
* for these GPUs to calculate bandwidth requirements.
*/
if (high_pixelclock_count) {
/* Work around flickering lines at the bottom edge
* of the screen when using a single 4K 60Hz monitor.
*/
disable_mclk_switching = true;
/* On Oland, we observe some flickering when two 4K 60Hz
* displays are connected, possibly because voltage is too low.
* Raise the voltage by requiring a higher SCLK.