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drm/vc4: Also power down the PLL core when resetting PHY

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The current reset code doesn't actually stop the hdmi output.
That makes it difficult for displays to handle a mode set.

Powering down the PLL does actually remove the hdmi signal
and makes mode sets more reliable

Signed-off-by: Dom Cobley <popcornmix@gmail.com>
This commit is contained in:
Dom Cobley
2024-08-13 17:18:51 +01:00
parent 4b09fb2475
commit e1cb424c35
1 changed files with 2 additions and 0 deletions
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2
drivers/gpu/drm/vc4/vc4_hdmi_phy.c
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@@ -137,6 +137,7 @@
#define VC6_HDMI_TX_PHY_PLL_REFCLK_REFCLK_SEL_CMOS BIT(13)
#define VC6_HDMI_TX_PHY_PLL_REFCLK_REFFRQ_MASK VC4_MASK(9, 0)
#define VC6_HDMI_TX_PHY_PLL_POST_KDIV_BYPASS_EN BIT(4)
#define VC6_HDMI_TX_PHY_PLL_POST_KDIV_CLK0_SEL_MASK VC4_MASK(3, 2)
#define VC6_HDMI_TX_PHY_PLL_POST_KDIV_KDIV_MASK VC4_MASK(1, 0)
@@ -947,6 +948,7 @@ static void vc6_hdmi_reset_phy(struct vc4_hdmi *vc4_hdmi)
HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0);
HDMI_WRITE(HDMI_TX_PHY_POWERUP_CTL, 0);
HDMI_WRITE(HDMI_TX_PHY_PLL_POST_KDIV, VC6_HDMI_TX_PHY_PLL_POST_KDIV_BYPASS_EN);
}
void vc6_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,