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dmaengine: bcm2835: HACK: Support DMA-Lite channels

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The BCM2712 has a DMA-Lite controller that is basically a BCM2835-style
DMA controller that supports 40 bits DMA addresses.

We need it for HDMI audio to work, but this breaks BCM2835-38 so we
should rework this later.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>

dmaengine: bcm2835: Fix dma driver for BCM2835-38

The previous commit broke support on older devices.
Make the breaking parts of patch conditional on
the device being used.

Fixes: 6e1856ac7c39 ("dmaengine: bcm2835: HACK: Support DMA-Lite channels")

Signed-off-by: Dom Cobley <popcornmix@gmail.com>
This commit is contained in:
Maxime Ripard
2023-04-13 16:52:19 +02:00
committed by Dom Cobley
parent e1ef110f2b
commit f93949993b
1 changed files with 16 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
drivers/dma/bcm2835-dma.c
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@@ -101,6 +101,7 @@ struct bcm2835_chan {
bool is_lite_channel;
bool is_40bit_channel;
bool is_2712;
};
struct bcm2835_desc {
@@ -549,7 +550,11 @@ static struct bcm2835_desc *bcm2835_dma_create_cb_chain(
control_block->info = info;
control_block->src = src;
control_block->dst = dst;
control_block->stride = 0;
if (c->is_2712)
control_block->stride = (upper_32_bits(dst) << 8) |
upper_32_bits(src);
else
control_block->stride = 0;
control_block->next = 0;
}
@@ -574,7 +579,8 @@ static struct bcm2835_desc *bcm2835_dma_create_cb_chain(
d->cb_list[frame - 1].cb)->next_cb =
to_bcm2711_cbaddr(cb_entry->paddr);
if (frame && !c->is_40bit_channel)
d->cb_list[frame - 1].cb->next = cb_entry->paddr;
d->cb_list[frame - 1].cb->next = c->is_2712 ?
to_bcm2711_cbaddr(cb_entry->paddr) : cb_entry->paddr;
/* update src and dst and length */
if (src && (info & BCM2835_DMA_S_INC)) {
@@ -759,7 +765,10 @@ static void bcm2835_dma_start_desc(struct bcm2835_chan *c)
writel(BCM2711_DMA40_ACTIVE | BCM2711_DMA40_PROT | BCM2711_DMA40_CS_FLAGS(c->dreq),
c->chan_base + BCM2711_DMA40_CS);
} else {
writel(d->cb_list[0].paddr, c->chan_base + BCM2835_DMA_ADDR);
writel(BIT(31), c->chan_base + BCM2835_DMA_CS);
writel(c->is_2712 ? to_bcm2711_cbaddr(d->cb_list[0].paddr) : d->cb_list[0].paddr,
c->chan_base + BCM2835_DMA_ADDR);
writel(BCM2835_DMA_ACTIVE | BCM2835_DMA_CS_FLAGS(c->dreq),
c->chan_base + BCM2835_DMA_CS);
}
@@ -1132,7 +1141,8 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
d->cb_list[frames - 1].cb)->next_cb =
to_bcm2711_cbaddr(d->cb_list[0].paddr);
else
d->cb_list[d->frames - 1].cb->next = d->cb_list[0].paddr;
d->cb_list[d->frames - 1].cb->next = c->is_2712 ?
to_bcm2711_cbaddr(d->cb_list[0].paddr) : d->cb_list[0].paddr;
return vchan_tx_prep(&c->vc, &d->vd, flags);
}
@@ -1199,6 +1209,8 @@ static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id,
else if (readl(c->chan_base + BCM2835_DMA_DEBUG) &
BCM2835_DMA_DEBUG_LITE)
c->is_lite_channel = true;
if (d->cfg_data->dma_mask == DMA_BIT_MASK(40))
c->is_2712 = true;
return 0;
}