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bnxt_en: Update firmware interface spec to 1.10.3.85
The major change is the new firmware command to flush the FW debug logs to the host backing store context memory buffers. Reviewed-by: Hongguang Gao <hongguang.gao@broadcom.com> Reviewed-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com> Signed-off-by: Michael Chan <michael.chan@broadcom.com> Link: https://patch.msgid.link/20241115151438.550106-2-michael.chan@broadcom.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Michael Chan
committed by
Jakub Kicinski
Jakub Kicinski
parent
84ad482560
commit
ff00bcc9ec
@@ -42,6 +42,10 @@ struct hwrm_resp_hdr {
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#define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL
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#define TLV_TYPE_QUERY_ROCE_CC_GEN2 0x6UL
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#define TLV_TYPE_MODIFY_ROCE_CC_GEN2 0x7UL
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#define TLV_TYPE_QUERY_ROCE_CC_GEN1_EXT 0x8UL
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#define TLV_TYPE_MODIFY_ROCE_CC_GEN1_EXT 0x9UL
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#define TLV_TYPE_QUERY_ROCE_CC_GEN2_EXT 0xaUL
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#define TLV_TYPE_MODIFY_ROCE_CC_GEN2_EXT 0xbUL
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#define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL
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#define TLV_TYPE_ENGINE_CKV_IV 0x8003UL
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#define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL
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@@ -509,6 +513,7 @@ struct cmd_nums {
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#define HWRM_TFC_IF_TBL_GET 0x399UL
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#define HWRM_TFC_TBL_SCOPE_CONFIG_GET 0x39aUL
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#define HWRM_TFC_RESC_USAGE_QUERY 0x39bUL
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#define HWRM_TFC_GLOBAL_ID_FREE 0x39cUL
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#define HWRM_SV 0x400UL
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#define HWRM_DBG_SERDES_TEST 0xff0eUL
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#define HWRM_DBG_LOG_BUFFER_FLUSH 0xff0fUL
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@@ -624,8 +629,8 @@ struct hwrm_err_output {
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#define HWRM_VERSION_MAJOR 1
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#define HWRM_VERSION_MINOR 10
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#define HWRM_VERSION_UPDATE 3
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#define HWRM_VERSION_RSVD 68
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#define HWRM_VERSION_STR "1.10.3.68"
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#define HWRM_VERSION_RSVD 85
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#define HWRM_VERSION_STR "1.10.3.85"
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/* hwrm_ver_get_input (size:192b/24B) */
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struct hwrm_ver_get_input {
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@@ -1302,6 +1307,43 @@ struct hwrm_async_event_cmpl_error_report {
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#define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0
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};
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/* hwrm_async_event_cmpl_dbg_buf_producer (size:128b/16B) */
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struct hwrm_async_event_cmpl_dbg_buf_producer {
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__le16 type;
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#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_MASK 0x3fUL
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#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_SFT 0
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#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_HWRM_ASYNC_EVENT 0x2eUL
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#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_LAST ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_HWRM_ASYNC_EVENT
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__le16 event_id;
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#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_DBG_BUF_PRODUCER 0x4cUL
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#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_LAST ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_DBG_BUF_PRODUCER
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__le32 event_data2;
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#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA2_CURR_OFF_MASK 0xffffffffUL
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#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA2_CURR_OFF_SFT 0
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u8 opaque_v;
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#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_V 0x1UL
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#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_OPAQUE_MASK 0xfeUL
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#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_OPAQUE_SFT 1
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u8 timestamp_lo;
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__le16 timestamp_hi;
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__le32 event_data1;
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#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_MASK 0xffffUL
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#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SFT 0
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#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SRT_TRACE 0x0UL
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#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SRT2_TRACE 0x1UL
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#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CRT_TRACE 0x2UL
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#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CRT2_TRACE 0x3UL
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#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_RIGP0_TRACE 0x4UL
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#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_L2_HWRM_TRACE 0x5UL
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#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_ROCE_HWRM_TRACE 0x6UL
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#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA0_TRACE 0x7UL
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#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA1_TRACE 0x8UL
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#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA2_TRACE 0x9UL
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#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_RIGP1_TRACE 0xaUL
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#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_AFM_KONG_HWRM_TRACE 0xbUL
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#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_LAST ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_AFM_KONG_HWRM_TRACE
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};
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/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
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struct hwrm_async_event_cmpl_hwrm_error {
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__le16 type;
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@@ -1864,7 +1906,10 @@ struct hwrm_func_qcaps_output {
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__le32 roce_vf_max_gid;
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__le32 flags_ext3;
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#define FUNC_QCAPS_RESP_FLAGS_EXT3_RM_RSV_WHILE_ALLOC_CAP 0x1UL
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u8 unused_3[7];
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#define FUNC_QCAPS_RESP_FLAGS_EXT3_REQUIRE_L2_FILTER 0x2UL
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#define FUNC_QCAPS_RESP_FLAGS_EXT3_MAX_ROCE_VFS_SUPPORTED 0x4UL
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__le16 max_roce_vfs;
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u8 unused_3[5];
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u8 valid;
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};
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@@ -2253,17 +2298,18 @@ struct hwrm_func_cfg_input {
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#define FUNC_CFG_REQ_FLAGS2_KTLS_KEY_CTX_ASSETS_TEST 0x1UL
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#define FUNC_CFG_REQ_FLAGS2_QUIC_KEY_CTX_ASSETS_TEST 0x2UL
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__le32 enables2;
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#define FUNC_CFG_REQ_ENABLES2_KDNET 0x1UL
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#define FUNC_CFG_REQ_ENABLES2_DB_PAGE_SIZE 0x2UL
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#define FUNC_CFG_REQ_ENABLES2_QUIC_TX_KEY_CTXS 0x4UL
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#define FUNC_CFG_REQ_ENABLES2_QUIC_RX_KEY_CTXS 0x8UL
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#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_AV_PER_VF 0x10UL
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#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_CQ_PER_VF 0x20UL
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#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_MRW_PER_VF 0x40UL
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#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_QP_PER_VF 0x80UL
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#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_SRQ_PER_VF 0x100UL
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#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_GID_PER_VF 0x200UL
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#define FUNC_CFG_REQ_ENABLES2_XID_PARTITION_CFG 0x400UL
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#define FUNC_CFG_REQ_ENABLES2_KDNET 0x1UL
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#define FUNC_CFG_REQ_ENABLES2_DB_PAGE_SIZE 0x2UL
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#define FUNC_CFG_REQ_ENABLES2_QUIC_TX_KEY_CTXS 0x4UL
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#define FUNC_CFG_REQ_ENABLES2_QUIC_RX_KEY_CTXS 0x8UL
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#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_AV_PER_VF 0x10UL
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#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_CQ_PER_VF 0x20UL
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#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_MRW_PER_VF 0x40UL
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#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_QP_PER_VF 0x80UL
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#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_SRQ_PER_VF 0x100UL
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#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_GID_PER_VF 0x200UL
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#define FUNC_CFG_REQ_ENABLES2_XID_PARTITION_CFG 0x400UL
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#define FUNC_CFG_REQ_ENABLES2_PHYSICAL_SLOT_NUMBER 0x800UL
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u8 port_kdnet_mode;
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#define FUNC_CFG_REQ_PORT_KDNET_MODE_DISABLED 0x0UL
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#define FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED 0x1UL
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@@ -2281,7 +2327,7 @@ struct hwrm_func_cfg_input {
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#define FUNC_CFG_REQ_DB_PAGE_SIZE_2MB 0x9UL
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#define FUNC_CFG_REQ_DB_PAGE_SIZE_4MB 0xaUL
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#define FUNC_CFG_REQ_DB_PAGE_SIZE_LAST FUNC_CFG_REQ_DB_PAGE_SIZE_4MB
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u8 unused_1[2];
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__le16 physical_slot_number;
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__le32 num_ktls_tx_key_ctxs;
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__le32 num_ktls_rx_key_ctxs;
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__le32 num_quic_tx_key_ctxs;
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@@ -3683,7 +3729,7 @@ struct hwrm_func_ptp_ext_qcfg_output {
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u8 valid;
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};
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/* hwrm_func_backing_store_cfg_v2_input (size:448b/56B) */
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/* hwrm_func_backing_store_cfg_v2_input (size:512b/64B) */
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struct hwrm_func_backing_store_cfg_v2_input {
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__le16 req_type;
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__le16 cmpl_ring;
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@@ -3721,6 +3767,7 @@ struct hwrm_func_backing_store_cfg_v2_input {
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#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CA1_TRACE 0x27UL
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#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CA2_TRACE 0x28UL
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#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RIGP1_TRACE 0x29UL
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#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_AFM_KONG_HWRM_TRACE 0x2aUL
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#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 0xffffUL
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#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID
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__le16 instance;
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@@ -3752,6 +3799,9 @@ struct hwrm_func_backing_store_cfg_v2_input {
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__le32 split_entry_1;
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__le32 split_entry_2;
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__le32 split_entry_3;
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__le32 enables;
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#define FUNC_BACKING_STORE_CFG_V2_REQ_ENABLES_NEXT_BS_OFFSET 0x1UL
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__le32 next_bs_offset;
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};
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/* hwrm_func_backing_store_cfg_v2_output (size:128b/16B) */
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@@ -3802,6 +3852,7 @@ struct hwrm_func_backing_store_qcfg_v2_input {
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#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CA1_TRACE 0x27UL
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#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CA2_TRACE 0x28UL
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#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RIGP1_TRACE 0x29UL
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#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_AFM_KONG_HWRM_TRACE 0x2aUL
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#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 0xffffUL
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#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID
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__le16 instance;
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@@ -3963,6 +4014,7 @@ struct hwrm_func_backing_store_qcaps_v2_input {
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#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA1_TRACE 0x27UL
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#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA2_TRACE 0x28UL
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#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP1_TRACE 0x29UL
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#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_AFM_KONG_HWRM_TRACE 0x2aUL
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#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 0xffffUL
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#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID
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u8 rsvd[6];
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@@ -4005,6 +4057,7 @@ struct hwrm_func_backing_store_qcaps_v2_output {
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#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CA1_TRACE 0x27UL
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#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CA2_TRACE 0x28UL
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#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RIGP1_TRACE 0x29UL
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#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_AFM_KONG_HWRM_TRACE 0x2aUL
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#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 0xffffUL
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#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID
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__le16 entry_size;
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@@ -4014,6 +4067,8 @@ struct hwrm_func_backing_store_qcaps_v2_output {
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#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_DRIVER_MANAGED_MEMORY 0x4UL
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#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ROCE_QP_PSEUDO_STATIC_ALLOC 0x8UL
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#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_FW_DBG_TRACE 0x10UL
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#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_FW_BIN_DBG_TRACE 0x20UL
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#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_NEXT_BS_OFFSET 0x40UL
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__le32 instance_bit_map;
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u8 ctx_init_value;
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u8 ctx_init_offset;
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@@ -4034,7 +4089,8 @@ struct hwrm_func_backing_store_qcaps_v2_output {
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__le32 split_entry_1;
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__le32 split_entry_2;
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__le32 split_entry_3;
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u8 rsvd3[3];
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__le16 max_instance_count;
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u8 rsvd3;
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u8 valid;
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};
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@@ -4535,11 +4591,12 @@ struct hwrm_port_phy_qcfg_output {
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#define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEDR8 0x3dUL
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#define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEDR8
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u8 media_type;
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#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL
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#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL
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#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL
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#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL
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#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE
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#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL
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#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL
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#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL
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#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL
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#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_BACKPLANE 0x4UL
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#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_BACKPLANE
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u8 xcvr_pkg_type;
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#define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL
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#define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL
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@@ -4654,7 +4711,8 @@ struct hwrm_port_phy_qcfg_output {
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#define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB 0x2UL
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#define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB 0x4UL
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u8 link_down_reason;
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#define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_RF 0x1UL
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#define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_RF 0x1UL
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#define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_OTP_SPEED_VIOLATION 0x2UL
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__le16 support_speeds2;
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#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_1GB 0x1UL
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#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_10GB 0x2UL
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@@ -9241,20 +9299,22 @@ struct hwrm_fw_set_time_output {
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/* hwrm_struct_hdr (size:128b/16B) */
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struct hwrm_struct_hdr {
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__le16 struct_id;
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#define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL
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#define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL
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#define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL
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#define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL
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#define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL
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#define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL
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#define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL
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#define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL
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#define STRUCT_HDR_STRUCT_ID_PEER_MMAP 0x429UL
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#define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL
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#define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL
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#define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL
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#define STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 0xc8UL
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#define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_MSIX_PER_VF
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#define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL
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#define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL
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#define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL
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#define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL
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#define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL
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#define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL
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#define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL
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#define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL
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#define STRUCT_HDR_STRUCT_ID_PEER_MMAP 0x429UL
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#define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL
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#define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL
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#define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL
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#define STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 0xc8UL
|
||||
#define STRUCT_HDR_STRUCT_ID_UDCC_RTT_BUCKET_COUNT 0x12cUL
|
||||
#define STRUCT_HDR_STRUCT_ID_UDCC_RTT_BUCKET_BOUND 0x12dUL
|
||||
#define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_UDCC_RTT_BUCKET_BOUND
|
||||
__le16 len;
|
||||
u8 version;
|
||||
u8 count;
|
||||
@@ -9756,6 +9816,7 @@ struct hwrm_dbg_qcaps_output {
|
||||
#define DBG_QCAPS_RESP_FLAGS_COREDUMP_HOST_DDR 0x10UL
|
||||
#define DBG_QCAPS_RESP_FLAGS_COREDUMP_HOST_CAPTURE 0x20UL
|
||||
#define DBG_QCAPS_RESP_FLAGS_PTRACE 0x40UL
|
||||
#define DBG_QCAPS_RESP_FLAGS_REG_ACCESS_RESTRICTED 0x80UL
|
||||
u8 unused_1[3];
|
||||
u8 valid;
|
||||
};
|
||||
@@ -9996,6 +10057,43 @@ struct hwrm_dbg_ring_info_get_output {
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
/* hwrm_dbg_log_buffer_flush_input (size:192b/24B) */
|
||||
struct hwrm_dbg_log_buffer_flush_input {
|
||||
__le16 req_type;
|
||||
__le16 cmpl_ring;
|
||||
__le16 seq_id;
|
||||
__le16 target_id;
|
||||
__le64 resp_addr;
|
||||
__le16 type;
|
||||
#define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_SRT_TRACE 0x0UL
|
||||
#define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_SRT2_TRACE 0x1UL
|
||||
#define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CRT_TRACE 0x2UL
|
||||
#define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CRT2_TRACE 0x3UL
|
||||
#define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_RIGP0_TRACE 0x4UL
|
||||
#define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_L2_HWRM_TRACE 0x5UL
|
||||
#define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_ROCE_HWRM_TRACE 0x6UL
|
||||
#define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CA0_TRACE 0x7UL
|
||||
#define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CA1_TRACE 0x8UL
|
||||
#define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CA2_TRACE 0x9UL
|
||||
#define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_RIGP1_TRACE 0xaUL
|
||||
#define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_AFM_KONG_HWRM_TRACE 0xbUL
|
||||
#define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_LAST DBG_LOG_BUFFER_FLUSH_REQ_TYPE_AFM_KONG_HWRM_TRACE
|
||||
u8 unused_1[2];
|
||||
__le32 flags;
|
||||
#define DBG_LOG_BUFFER_FLUSH_REQ_FLAGS_FLUSH_ALL_BUFFERS 0x1UL
|
||||
};
|
||||
|
||||
/* hwrm_dbg_log_buffer_flush_output (size:128b/16B) */
|
||||
struct hwrm_dbg_log_buffer_flush_output {
|
||||
__le16 error_code;
|
||||
__le16 req_type;
|
||||
__le16 seq_id;
|
||||
__le16 resp_len;
|
||||
__le32 current_buffer_offset;
|
||||
u8 unused_1[3];
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
/* hwrm_nvm_read_input (size:320b/40B) */
|
||||
struct hwrm_nvm_read_input {
|
||||
__le16 req_type;
|
||||
@@ -10080,6 +10178,7 @@ struct hwrm_nvm_write_input {
|
||||
#define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL
|
||||
#define NVM_WRITE_REQ_FLAGS_BATCH_MODE 0x2UL
|
||||
#define NVM_WRITE_REQ_FLAGS_BATCH_LAST 0x4UL
|
||||
#define NVM_WRITE_REQ_FLAGS_SKIP_CRID_CHECK 0x8UL
|
||||
__le32 dir_item_length;
|
||||
__le32 offset;
|
||||
__le32 len;
|
||||
|
||||
Reference in New Issue
Block a user