Make the BCM2712's onboard GPIOs start at gpiochip10, marking them out
as system resources and preventing accidental use by existing Pi 5
code.
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
In the same way that other subsystems support the setting of device
id numbers from Device Tree aliases, allow gpiochip numbers to be
derived from "gpiochip<n>" aliases.
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
The corresponding driver implementation has seen sufficient testing,
so enable by default. Retain the dtparam so it can be turned off for test.
Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
Many HD44780 LCD displays are connected via very common I2C
GPIO expander.
We have an overlay for connecting the displays directly to GPIOs,
but not one for it connected via a backpack. Add such an overlay.
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
There is now an ssd1327-spi overlay, but it's of little use without
the corresponding display drivers. Add them as modules to the usual
defconfig files.
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
The DW SPI interface has a 16-bit clock divider, where the bottom bit
of the divisor must be 0. Limit how low the clock speed can go to
prevent the clock divider from being truncated, as that could lead to
a much higher clock rate than requested.
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
Ensure the transmit FIFO has emptied before ending the transfer by
dropping the TX threshold to 0 when the last byte has been pushed into
the FIFO. Include a similar fix for the non-IRQ paths.
See: https://github.com/raspberrypi/linux/issues/6285
Fixes: 6014649de7 ("spi: dw: Save bandwidth with the TMOD_TO feature")
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
Pi 0-3 have no deep colour support and only 24bpp output,
so max_bpc should remain as 8.
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Valid ranges for the I2S peripheral's FIFO configuration include a depth
of 16 - unconditionally setting the burst length to 16 with a fifo
threshold of size/2 will cause under/overflows.
For DMA engines with restricted capabilities the requested burst length
and FIFO thresholds need to be adjusted downward accordingly.
Both the RX and TX FIFOs operate on "less-than" thresholds. Setting the
TX threshold to fifo_size minus burst means the FIFO is kept nearly-full.
Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
Do an end-run around ASoC in lieu of not being able to easily find the
associated DMA controller capabilities.
Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
If the associated DMA controller has lower burst length support than the
level the FIFO is set to, then bytes will be left in the RX FIFO at the
end of a DMA block - requiring a round-trip through the timeout interrupt
handler rather than an end-of-block DMA interrupt.
Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
There's no real need to constrain MEM access widths to 32-bit (or
narrower), as the DMAC is intelligent enough to size memory accesses
appropriately. Wider accesses are more efficient.
Similarly, MEM burst lengths don't need to be a function of DEV burst
lengths - the DMAC packs/unpacks data into/from its internal channel
FIFOs appropriately. Longer accesses are more efficient.
However, the DMAC doesn't have complete support for unaligned accesses,
and blocks are always defined in integer multiples of SRC_WIDTH, so odd
source lengths or buffer alignments will prevent wide accesses being
used, as before.
There is an implicit requirement to limit requested DEV read burst
lengths to less than the hardware's maximum configured MSIZE - otherwise
RX data will be left over at the end of a block. There is no config
register that reports this value, so the AXI burst length parameter is
used to produce a facsimile of it. Warn if such a request arrives that
doesn't respect this.
Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
Disabling the peripheral resets controller state which has a dangerous
side-effect of disabling the DMA handshake interface while it is active.
This can cause DMA channels to hang.
The error recovery pathway will wait for DMA to stop and reset the chip
anyway, so mask further FIFO interrupts and let the transfer finish
gracefully.
Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
TMOD_RO is the receive-only mode that doesn't require data in the
transmit FIFO in order to generate clock cycles. Using TMOD_RO when the
device doesn't care about the data sent to it saves CPU time and memory
bandwidth.
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
TMOD_TO is the transmit-only mode that doesn't put data into the receive
FIFO. Using TMOD_TO when the user doesn't want the received data saves
CPU time and memory bandwidth.
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
We do NOT claim to support decoding in real-time for these levels,
but can transcode some content, and handle 1920x1200.
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Video encode can defer generating the header until the first
frame is presented, which allows it to take the colourspace
information from the frame rather than just the format.
Enable that for the V4L2 driver now that the firmware populates
all the parameters.
https://github.com/raspberrypi/firmware/issues/1885
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Automatic link power saving plus the ability of a root complex to buffer
pending posted write transfers (and consider them complete before being
transmitted on the wire) causes compression of updates to GPIO state.
The large bandwidth of a Gen 2 x4 link means the writes toggle state
inside RP1 as fast as it can go (~20MHz), which is bad for applications
wanting bitbash with at least a few microseconds of delay between
updates.
By tailoring IO access patterns to a special Root Complex register,
writes to GPIOs can be stalled until the link wakes - meaning all writes
end up with a reasonably consistent minimum pacing (~200ns).
Additionally, write barriers have no effect other than to arbitrarily
delay some writes by a small, variable amount - so remove the vast
majority of these in areas that could be hot-paths.
Although the IO memory is mapped with Device strongly-ordered semantics,
this doesn't prevent the splitter inside BCM2712 from letting an MMIO
read request to a GPIO register get ahead of the pacing writes to the
Root Complex register. So each pin state read must flush writes out to
the Outer-Shareable domain.
Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
The upstream Unicam driver needs a set of userland changes to get
libcamera to run, and those aren't written or merged yet.
Move the "brcm,bcm2835-unicam" compatible from the upstream driver
to the old downstream version so that users can run libcamera
against 6.10.
Once the libcamera changes have been merged this can be reverted
to use the upstream driver.
If using the non-legacy compatible then assume we want to use
media-controller API for configuration.
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Whilst the Unicam driver has now been upstreamed it only supports
configuration via Media Controller (not driven from the /dev/videoN
node), which makes life significantly harder for simple devices such
as mono sensors, and HDMI or analogue video to CSI2 bridge chips
(eg TC358743 and ADV7282M).
Fix up the downstream driver so that it builds, reinstate the links
from Kconfig and Makefile to it, and give it a new Kconfig name
(VIDEO_BCM2835_UNICAM_LEGACY).
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
To support 4 lanes, re-parent DPI clock source between DSI byteclock
(using the new "variable sources" defined in clk-rp1) and PLL_SYS.
This is to cover cases in which byteclock < pixclock <= 200MHz.
Tidying: All frequencies now in Hz (not kHz), where DSI speed is now
represented by byteclock to simplify arithmetic. Clamp DPI and byte
clocks to their legal ranges; fix up HSTX timeout to avoid an unsafe
assumption that it would return to LP state for every scanline.
Because of RP1's clock topology, the ratio between DSI and DPI clocks
may not be exact with 3 or 4 lanes, leading to slightly irregular
timings each time DSI switches between HS and LP states. Tweak to
inhibit LP during Horizontal BP when sync pulses were requested.
Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
Add a new class of clocks to RP1 to represent clock sources whose
frequency changes at run-time as a side-effect of some other driver.
Specifically this is for the two MIPI DSI byte-clock sources.
Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
Define two new RP1 clocks, representing the MIPI DSI byteclock
sources for the dividers used to generate MIPI[01] DPI pixel clocks.
(Previously they were represented by "fake" fixed clocks sources).
Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
The firmware advertises its features as a string of words separated by
spaces. Ensure that feature names are only matched in their entirety.
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
Command Queueing requires Write Cache and Power off Notification support
from the card - but using the write cache forms a contract with the host
whereby the card expects to be told about impending power-down.
The implication is that (for performance) the card can do unsafe things
with pending write data - including reordering what gets committed to
nonvolatile storage at what time.
Exposed SD slots and platforms powered by hotpluggable means (i.e.
Raspberry Pis) can't guarantee that surprise removal won't happen.
To limit the scope for cards to invent new ways to trash filesystems,
limit pending writes to 1 (equivalent to the non-CQ behaviour).
Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
fixup: mmc: restrict posted write counts for SD cards in CQ mode
Leaving card->max_posted_writes unintialised was a bad thing to do.
Also, cqe_enable is 1 if hsq is enabled as hsq substitutes the cqhci
implementation with its own.
Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
The snps,block-size DT property declares the maximum block size for each
channel of the dw-axi-dmac. However, the driver ignores these when
setting max_seg_size and uses MAX_BLOCK_SIZE (4096) instead.
To take advantage of the efficiencies of larger blocks, calculate the
minimum block size across all channels and use that instead.
See: https://github.com/raspberrypi/linux/issues/6256
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
The Raspberry Pi RP2040 GPIO bridge is an I2C-attached device exposing
both a Tx-only SPI controller, and a GPIO controller.
Due to the relative difference in transfer rates between standard-mode
I2C and SPI, the GPIO bridge makes use of 12 MiB of non-volatile storage
to cache repeated transfers. This cache is arranged in ~8 KiB blocks and
is addressed by the MD5 digest of the data contained therein.
Optionally, this driver is able to take advantage of Raspberry Pi RP1
GPIOs to achieve faster than I2C data transfer rates.
Signed-off-by: Richard Oliver <richard.oliver@raspberrypi.com>
Offset the backend dev-nodes starting at /dev/video20
onwards to maintain backward compatibility with the
pre-upstreamed kernel driver.
Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
The rework in fs/ntfs3: Reduce stack usage
changes log->page_size but doesn't change the associated
log->page_mask and log->page_bits.
That results in the bytes value in read_log_page
getting a negative value, which is bad when it is
passed to memcpy.
The kernel panic can be observed when connecting an
ntfs formatted drive that has previously been connected
to a Windows machine to a Raspberry Pi 5, which by defauilt
uses a 16K kernel pagesize.
Fixes: 865e7a7700 ("fs/ntfs3: Reduce stack usage")
Signed-off-by: Dom Cobley <popcornmix@gmail.com>
Recovery claims the MMC card so the card-detect work gets significantly
delayed - leading to lots of error recovery loops that can never do
anything but fail.
Explicitly detect the card after CQE has halted and bail if it's not
there.
Also ratelimit a not-very-descriptive warning - one occurrence in dmesg
is enough to signal that something is amiss.
Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
If the controller is being reset, then the CQE needs to be reset as well.
For removable cards, CQHCI_SSC1 must specify a polling mode (CBC=0)
otherwise it's possible that the controller stops emitting periodic
CMD13s on card removal, without raising an error status interrupt.
Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
The platform model originally handled the DMA mask. Now that
we are on the vchiq_bus we need to explicitly set this.
Signed-off-by: Kieran Bingham <kieran.bingham@ideasonboard.com>
The platform model originally handled the DMA mask. Now that
we are on the vchiq_bus we need to explicitly set this.
Signed-off-by: Kieran Bingham <kieran.bingham@ideasonboard.com>
The platform model originally handled the DMA mask. Now that
we are on the vchiq_bus we need to explicitly set this.
Signed-off-by: Kieran Bingham <kieran.bingham@ideasonboard.com>
Disabling tx_lpi or eee should not cause the value of tx_lpi_timer to
be lost, even though it is not useful until they are re-enabled.
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
Add two new DT properties:
* microchip,eee-enabled - a boolean to enable EEE
* microchip,tx-lpi-timer - time in microseconds to wait before entering
low power state
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
This gains about 8-12% sequential write speed with the fastest SD/eMMC
cards, and Class A1/A2 card sequential performance is only assured with
a 4MiB write length.
Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
SD cards perform cache flushes by a CMD49 extension register write -
which needs to be started from the SDHCI command/argument registers and
not a CQHCI slot.
Host access to SD/CQ registers should be exclusive to one or the other,
so issue a halt before doing the command.
Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
