Joakim Zhang cbcacc9c06 drivers/perf: fsl_imx8_ddr: Correct the CLEAR bit definition ...

[ Upstream commit 049d919168 ]

When disabling a counter from ddr_perf_event_stop(), the counter value
is reset to 0 at the same time.

Preserve the counter value by performing a read-modify-write of the
PMU register and clearing only the enable bit.

Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

2020-03-25 08:26:56 +01:00

18 KiB

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