Andrew Lunn 4b8f7a11c9 ARM: MM: Add DT binding for Feroceon L2 cache ...

Instantiate the L2 cache from DT. Indicate in DT where the cache
control register is so that it is possible to enable/disable write
through on the CPU.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

2014-02-22 20:43:49 +00:00

398 B

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